Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64095 )
Change subject: nb/intel/gm45: Enable 64bit support ......................................................................
nb/intel/gm45: Enable 64bit support
This patch does the following: - Allow selecting 64bit from Kconfig - Fix up integer to pointer conversion that gcc complains about - Add a buildtest target in configs
Tested on Thinkpad X200: boots fine to the payload
Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M configs/config.lenovo_t400_vboot_and_debug M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c 7 files changed, 16 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/64095/1
diff --git a/configs/config.lenovo_t400_vboot_and_debug b/configs/config.lenovo_t400_vboot_and_debug index 2923f94..39c17e6 100644 --- a/configs/config.lenovo_t400_vboot_and_debug +++ b/configs/config.lenovo_t400_vboot_and_debug @@ -12,3 +12,4 @@ CONFIG_DEBUG_ADA_CODE=y CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y CONFIG_VBOOT=y +CONFIG_USE_EXP_X86_64_SUPPORT=y diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 3f632a1..c186f01 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -12,6 +12,7 @@ select INTEL_EDID select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF + select HAVE_EXP_X86_64_SUPPORT
config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 4199f8b..46c8db3 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -37,7 +37,7 @@
/* setup somewhere */ pci_or_config16(igd, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0); + void *bar = (void *)(uintptr_t)pci_read_config32(igd, PCI_BASE_ADDRESS_0);
/* clear GTT, 2MB is enough (and should be safe) */ memset(bar, 0, 2<<20); diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 60fd635..315c54c 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -93,7 +93,7 @@
/* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem;
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 35d71c0..4196edf 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1577,15 +1577,15 @@ const u32 rankaddr = raminit_get_rank_addr(ch, r); printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", rankaddr); mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(2)); - read32((u32 *)(rankaddr | WL)); + read32p(rankaddr | WL); mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(3)); - read32((u32 *)rankaddr); + read32p(rankaddr); mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(1)); - read32((u32 *)(rankaddr | ODT_120OHMS | ODS_34OHMS)); + read32p(rankaddr | ODT_120OHMS | ODS_34OHMS); mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_SET_MREG); - read32((u32 *)(rankaddr | WR | DLL1 | CAS | INTERLEAVED)); + read32p(rankaddr | WR | DLL1 | CAS | INTERLEAVED); mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_SET_MREG); - read32((u32 *)(rankaddr | WR | CAS | INTERLEAVED)); + read32p(rankaddr | WR | CAS | INTERLEAVED); } }
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index be614ae..d3571df 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -96,7 +96,7 @@ for (i = 0; i < addresses->count; ++i) { unsigned int offset; for (offset = lane_offset; offset < 320; offset += 8) { - const u32 read = read32((u32 *)(addresses->addr[i] + offset)); + const u32 read = read32p(addresses->addr[i] + offset); const u32 good = read_training_schedule[offset >> 3]; if ((read & lane_mask) != (good & lane_mask)) return 0; @@ -211,7 +211,7 @@ /* Write test pattern. */ unsigned int offset; for (offset = 0; offset < 320; offset += 4) - write32((u32 *)(addresses.addr[i] + offset), + write32p(addresses.addr[i] + offset, read_training_schedule[offset >> 3]); }
@@ -419,18 +419,18 @@ unsigned int off; for (off = 0; off < 640; off += 8) { const u32 pattern = write_training_schedule[off >> 3]; - write32((u32 *)(addr + off), pattern); - write32((u32 *)(addr + off + 4), pattern); + write32p(addr + off, pattern); + write32p(addr + off + 4, pattern); }
mchbar_setbits8(0x78, 1);
for (off = 0; off < 640; off += 8) { const u32 good = write_training_schedule[off >> 3]; - const u32 read1 = read32((u32 *)(addr + off)); + const u32 read1 = read32p(addr + off); if ((read1 & masks[0]) != (good & masks[0])) goto _bad_timing_out; - const u32 read2 = read32((u32 *)(addr + off + 4)); + const u32 read2 = read32p(addr + off + 4); if ((read2 & masks[1]) != (good & masks[1])) goto _bad_timing_out; } diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 1d20746..6ca8013 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -128,7 +128,7 @@ mchbar_setbits32(mchbar, 1 << 9);
/* Read from this channel. */ - read32((u32 *)raminit_get_rank_addr(channel, 0)); + read32p(raminit_get_rank_addr(channel, 0));
mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4); return mchbar_read32(mchbar) & (1 << 30);