EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35206 )
Change subject: lib/spd_bin: Extend DDR4 spd information ......................................................................
lib/spd_bin: Extend DDR4 spd information
From DDR4 SPD spec:
Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved
Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved
Separate DDR3 and DDR4 banks. And extened rows, cols and ranks.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 --- M src/lib/spd_bin.c 1 file changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35206/1
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 1598ff1..e2a811a 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -36,10 +36,11 @@ void print_spd_info(uint8_t spd[]) { const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; - const int spd_rows[8] = {12, 13, 14, 15, 16, 17, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, 17, 18, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; char spd_name[DDR4_SPD_PART_LEN+1] = { 0 }; @@ -74,6 +75,7 @@ memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); spd_name[DDR4_SPD_PART_LEN] = 0; ranks = (spd[SPD_ORGANIZATION] >> 3) & 7; + banks = ddr4_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; devw = spd_devw[spd[12] & 7]; busw = spd_busw[spd[13] & 7]; break;