Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58924 )
Change subject: intel/strago: Fix some CHROMEOS guards ......................................................................
intel/strago: Fix some CHROMEOS guards
Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/chromeos.c 2 files changed, 6 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/58924/1
diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index 21ae380..511a9b9 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -2,11 +2,10 @@
bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
-romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +all-y += chromeos.c
-ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-y += ec.c +ramstage-y += gpio.c ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 1a945eb..0fd63c8 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -23,14 +23,13 @@ int get_write_protect_state(void) { /* - * The vboot loader queries this function in romstage. The GPIOs have + * This function might get queried early in romstage. The GPIOs have * not been set up yet as that configuration is done in ramstage. * Configuring this GPIO as input so that there isn't any ambiguity * in the reading. */ -#if ENV_ROMSTAGE - gpio_input_pullup(WP_GPIO); -#endif + if (ENV_ROMSTAGE_OR_BEFORE) + gpio_input_pullup(WP_GPIO);
/* WP is enabled when the pin is reading high. */ return !!gpio_get(WP_GPIO);