[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update chip files

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )

Change subject: soc/intel/tigerlake: Update chip files
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Patch Set 33: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/37783/33/src/soc/intel/tigerlake/Kc... 
File src/soc/intel/tigerlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/37783/33/src/soc/intel/tigerlake/Kc... 
PS33, Line 120: default 7 if SOC_INTEL_TIGERLAKE
              : 	default 16 if SOC_INTEL_JASPERLAKE
What is this based on? I think FSP allows maximum 16 entries for ClkReq and ClkSrc. Probably, the one for TGL is based on what is really present in the SoC? However, the one for JSL doesn't seem to be doing the same thing?