Hello Naresh Solanki, Subrata Banik, Balaji Manigandan, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/25236
to review the following change.
Change subject: mainboard/intel/coffeelake_rvp: Enable LAN CLK REQ and CLK USAGE ......................................................................
mainboard/intel/coffeelake_rvp: Enable LAN CLK REQ and CLK USAGE
Change-Id: I4058393c6ab0108b72882dbb81bb87024479b261 Signed-off-by: Ng Kin Wai kin.wai.ng@intel.com --- M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb 1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/25236/1
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 736abec..1b779d9 100755 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -54,10 +54,11 @@
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[2]" = "0xff" #NOT_USE register "PcieClkSrcUsage[3]" = "14" register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[5]" = "1" + register "PcieClkSrcUsage[9]" = "PCIE_CLK_LAN"
register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[1]" = "1" @@ -65,6 +66,7 @@ register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcClkReq[9]" = "9"
# Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1"