[coreboot-gerrit] Change in coreboot[master]: Cezanne FSP wrapper: Add UPD entry for eDP tunning

[Bao Zheng (Code Review)]

Attention is currently required from: Zheng Bao.
Hello Zheng Bao,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/59918

to review the following change.

Change subject: Cezanne FSP wrapper: Add UPD entry for eDP tunning
......................................................................

Cezanne FSP wrapper: Add UPD entry for eDP tunning

BUG=b:203061533

Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac
Signed-off-by: Zheng Bao 
---
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fsp_m_params.c
M src/vendorcode/amd/fsp/cezanne/FspmUpd.h
3 files changed, 31 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/59918/1

diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index 850d1bb..8ae62a5 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -105,6 +105,19 @@

uint8_t usb_phy_custom;
    struct usb_phy_config usb_phy;
+
+	/* eDP phy tuning settings */
+	uint8_t edp_phy_override;
+	/* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */
+	uint8_t edp_physel;
+
+	struct {
+		uint8_t dp_vs_pemph_level;
+		uint8_t tx_eq_main;
+		uint8_t tx_eq_pre;
+		uint8_t tx_eq_post;
+		uint8_t tx_vboost_lvl;
+	} edp_tuningset;
 };

#endif /* CEZANNE_CHIP_H */
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index 51e04e1..92debe3 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -157,6 +157,16 @@
    	mcfg->usb_phy = NULL;
    }

+	if (config->edp_phy_override) {
+		mcfg->edp_phy_override = config->edp_phy_override;
+		mcfg->edp_physel = config->edp_physel;
+		mcfg->dp_vs_pemph_level = config->edp_tuningset.dp_vs_pemph_level;
+		mcfg->tx_eq_main = config->edp_tuningset.tx_eq_main;
+		mcfg->tx_eq_pre = config->edp_tuningset.tx_eq_pre;
+		mcfg->tx_eq_post = config->edp_tuningset.tx_eq_post;
+		mcfg->tx_vboost_lvl = config->edp_tuningset.tx_vboost_lvl;
+	}
+
    fsp_fill_pcie_ddi_descriptors(mcfg);
    fsp_assign_ioapic_upds(mcfg);
    mb_pre_fspm();
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
index f21ca42..7cee318 100644
--- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
@@ -95,7 +95,14 @@
    /** Offset 0x04D3**/	uint32_t                    telemetry_vddcrsocOffset;
    /** Offset 0x04D7**/	uint8_t                     UnusedUpdSpace1;
    /** Offset 0x04D8**/	struct usb_phy_config       *usb_phy;
-	/** Offset 0x04DC**/	uint8_t                     UnusedUpdSpace2[292];
+	/** Offset 0x04DC**/	uint8_t                     edp_phy_override;
+	/** Offset 0x04DD**/	uint8_t                     edp_physel;
+	/** Offset 0x04DE**/	uint8_t                     dp_vs_pemph_level;
+	/** Offset 0x04DF**/	uint8_t                     tx_eq_main;
+	/** Offset 0x04E0**/	uint8_t                     tx_eq_pre;
+	/** Offset 0x04E1**/	uint8_t                     tx_eq_post;
+	/** Offset 0x04E2**/	uint8_t                     tx_vboost_lvl;
+	/** Offset 0x04E3**/	uint8_t                     UnusedUpdSpace2[285];
    /** Offset 0x0600**/	uint16_t                    UpdTerminator;
 } FSP_M_CONFIG;