Marc Jones has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45217 )
Change subject: soc/intel/xeon_sp: Use common ASL code for xeon_sp ......................................................................
soc/intel/xeon_sp: Use common ASL code for xeon_sp
Move and use the common xeon_sp/cpx/acpi asl for skx/. There were only minor whitespace differences between the directories.
Update the mainboards to build the moved files.
TiogaPass coreboot.rom checked with BUILD_TIMELESS.
Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b Signed-off-by: Marc Jones marcjones@sysproconsulting.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217 Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Jay Talbott JayTalbott@sysproconsulting.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/cedarisland_crb/dsdt.asl M src/mainboard/ocp/deltalake/dsdt.asl M src/mainboard/ocp/tiogapass/dsdt.asl R src/soc/intel/xeon_sp/acpi/globalnvs.asl R src/soc/intel/xeon_sp/acpi/iiostack.asl R src/soc/intel/xeon_sp/acpi/pci_irq.asl R src/soc/intel/xeon_sp/acpi/southcluster.asl R src/soc/intel/xeon_sp/acpi/uncore.asl R src/soc/intel/xeon_sp/acpi/uncore_irq.asl D src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl D src/soc/intel/xeon_sp/skx/acpi/iiostack.asl D src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl D src/soc/intel/xeon_sp/skx/acpi/uncore.asl D src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl 14 files changed, 5 insertions(+), 827 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Angel Pons: Looks good to me, approved Jay Talbott: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 407ee37..72a0ec1 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -21,7 +21,7 @@ { Device (PCI0) { - #include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl> + #include <soc/intel/xeon_sp/acpi/southcluster.asl> #include <soc/intel/common/block/acpi/acpi/lpc.asl>
} diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index 4d784f3..9fff558 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -14,12 +14,12 @@ #include "acpi/platform.asl"
// global NVS and variables - #include <soc/intel/xeon_sp/cpx/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
// CPX-SP ACPI tables - #include <soc/intel/xeon_sp/cpx/acpi/uncore.asl> + #include <soc/intel/xeon_sp/acpi/uncore.asl>
// LPC related entries Scope (_SB.PC00) diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index bd31251..769396f 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -15,12 +15,12 @@ #include "acpi/platform.asl"
// global NVS and variables - #include <soc/intel/xeon_sp/skx/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
// Xeon-SP ACPI tables Scope (_SB) { - #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> + #include <soc/intel/xeon_sp/acpi/uncore.asl> } } diff --git a/src/soc/intel/xeon_sp/cpx/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/globalnvs.asl rename to src/soc/intel/xeon_sp/acpi/globalnvs.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/iiostack.asl rename to src/soc/intel/xeon_sp/acpi/iiostack.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/acpi/pci_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/pci_irq.asl rename to src/soc/intel/xeon_sp/acpi/pci_irq.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/southcluster.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/southcluster.asl rename to src/soc/intel/xeon_sp/acpi/southcluster.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/uncore.asl b/src/soc/intel/xeon_sp/acpi/uncore.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/uncore.asl rename to src/soc/intel/xeon_sp/acpi/uncore.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/acpi/uncore_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl rename to src/soc/intel/xeon_sp/acpi/uncore_irq.asl diff --git a/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl deleted file mode 100644 index 8e4456f..0000000 --- a/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - - -/* Global Variables */ - -Name(\PICM, 0) // IOAPIC/8259 - -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - PCNT, 8, // 0x11 - Processor count - TPMP, 8, // 0x12 - TPM Present and Enabled - TLVL, 8, // 0x13 - Throttle Level - PPCM, 8, // 0x14 - Maximum P-state usable by OS - PM1I, 64, // 0x15 - PM1 wake status bit - GPEI, 64, // 0x1D - GPE wake status bit - U2WE, 16, // 0x25 - USB2 Wake Enable Bitmap - U3WE, 8, // 0x27 - USB3 Wake Enable Bitmap - - - /* Device Config */ - Offset (0x30), - S5U0, 8, // 0x30 - Enable USB0 in S5 - S5U1, 8, // 0x31 - Enable USB1 in S5 - S3U0, 8, // 0x32 - Enable USB0 in S3 - S3U1, 8, // 0x33 - Enable USB1 in S3 - TACT, 8, // 0x34 - Thermal Active trip point - TPSV, 8, // 0x35 - Thermal Passive trip point - TCRT, 8, // 0x36 - Thermal Critical trip point - DPTE, 8, // 0x37 - Enable DPTF - - /* Base addresses */ - Offset (0x50), - CMEM, 32, // 0x50 - CBMEM TOC - TOLM, 32, // 0x54 - Top of Low Memory - CBMC, 32, // 0x58 - coreboot mem console pointer - MMOB, 32, // 0x5C - MMIO Base Low Base - MMOL, 32, // 0x60 - MMIO Base Low Limit - MMHB, 64, // 0x64 - MMIO Base High Base - MMHL, 64, // 0x6C - MMIO Base High Limit - TSGB, 32, // 0x74 - TSEG Base - TSSZ, 32, // 0x78 - TSEG Size -} diff --git a/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl b/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl deleted file mode 100644 index 964be3c..0000000 --- a/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#define MAKE_IIO_DEV(id,rt) \ - Device (PC##id) \ - { \ - Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) \ - Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) \ - Name (_UID, 0x##id) \ - Method (_PRT, 0, NotSerialized) \ - { \ - If (PICM) \ - { \ - Return (_SB_.AR##rt) \ - } \ - Return (_SB_.PR##rt) \ - } \ - External(_SB.RT##id) \ - Method (_CRS, 0, NotSerialized) \ - { \ - Return (_SB.RT##id) \ - } \ - Name (SUPP, 0x00) \ - Name (CTRL, 0x00) \ - Name (_PXM, 0x00) /* _PXM: Device Proximity */ \ - Method (_OSC, 4, NotSerialized) \ - { \ - CreateDWordField (Arg3, 0x00, CDW1) \ - If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) \ - { \ - CreateDWordField (Arg3, 0x04, CDW2) \ - If ((Arg2 > 0x02)) \ - { \ - CreateDWordField (Arg3, 0x08, CDW3) \ - } \ - SUPP = CDW2 \ - CTRL = CDW3 \ - If ((AHPE || ((SUPP & 0x16) != 0x16))) \ - { \ - CTRL &= 0x1E \ - Sleep (0x03E8) \ - } \ - /* Never allow SHPC (no SHPC controller in system) */ \ - CTRL &= 0x1D \ - /* Disable Native PCIe AER handling from OS */ \ - CTRL &= 0x17 \ - If ((Arg1 != One)) /* unknown revision */ \ - { \ - CDW1 |= 0x08 \ - } \ - If ((CDW3 != CTRL)) /* capabilities bits were masked */ \ - { \ - CDW1 |= 0x10 \ - } \ - CDW3 = CTRL \ - Return (Arg3) \ - } \ - Else \ - { \ - /* indicate unrecognized UUID */ \ - CDW1 |= 0x04 \ - IO80 = 0xEE \ - Return (Arg3) \ - } \ - } \ - } - -MAKE_IIO_DEV(00, 00) -MAKE_IIO_DEV(01, 10) -MAKE_IIO_DEV(02, 20) -MAKE_IIO_DEV(03, 28) - -#if MAX_SOCKET > 1 -MAKE_IIO_DEV(06, 40) -MAKE_IIO_DEV(07, 50) -MAKE_IIO_DEV(08, 60) -MAKE_IIO_DEV(09, 68) -#endif diff --git a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl deleted file mode 100644 index b2a2ebf..0000000 --- a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Refer to Intel® C620 Series Chipset Platform Controller Hub EDS section 20.11 - * CONFIG_PCR_BASE_ADDRESS 0xfd000000 0x3100 - * (0xfd000000 | ((uint8_t)(0xC4) << 16) | (uint16_t)(0x3100) = 0xFDC43100 - * - * PIRQ routing control is in PCR ITSS region. - */ - -OperationRegion (ITSS, SystemMemory, PCR_ITSS_PIRQA_ROUT + - CONFIG_PCR_BASE_ADDRESS + (PID_ITSS << PCR_PORTID_SHIFT), 8) -Field (ITSS, ByteAcc, NoLock, Preserve) -{ - PIRA, 8, /* PIRQA Routing Control */ - PIRB, 8, /* PIRQB Routing Control */ - PIRC, 8, /* PIRQC Routing Control */ - PIRD, 8, /* PIRQD Routing Control */ - PIRE, 8, /* PIRQE Routing Control */ - PIRF, 8, /* PIRQF Routing Control */ - PIRG, 8, /* PIRQG Routing Control */ - PIRH, 8, /* PIRQH Routing Control */ -} - -Name (IREN, 0x80) /* Interrupt Routing Enable */ -Name (IREM, 0x0f) /* Interrupt Routing Mask */ - -Name (PRSA, ResourceTemplate () -{ - IRQ (Level, ActiveLow, Shared, ) - {3,4,5,6,7,10,11,12,14,15} -}) -Alias (PRSA, PRSB) -Name (PRSC, ResourceTemplate () -{ - IRQ (Level, ActiveLow, Shared, ) - {3,4,5,6,10,11,12,14,15} -}) -Alias (PRSC, PRSD) -Alias (PRSA, PRSE) -Alias (PRSA, PRSF) -Alias (PRSA, PRSG) -Alias (PRSA, PRSH) - -#define MAKE_LINK_DEV(id,uid) \ - Device (LNK##id) \ - { \ - Name (_HID, EISAID ("PNP0C0F")) \ - Name (_UID, ##uid) \ - Method (_PRS, 0, NotSerialized) \ - { \ - Return (PRS##id) \ - } \ - Method (_CRS, 0, Serialized) \ - { \ - Name (RTLA, ResourceTemplate () \ - { \ - IRQ (Level, ActiveLow, Shared) {} \ - }) \ - CreateWordField (RTLA, 1, IRQ0) \ - Store (Zero, IRQ0) \ - \ - /* Set the bit from PIRQ Routing Register */ \ - ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \ - Return (RTLA) \ - } \ - Method (_SRS, 1, Serialized) \ - { \ - CreateWordField (Arg0, 1, IRQ0) \ - FindSetRightBit (IRQ0, Local0) \ - Decrement (Local0) \ - Store (Local0, ^^PIR##id) \ - } \ - Method (_STA, 0, Serialized) \ - { \ - If (And (^^PIR##id, ^^IREN)) { \ - Return (0x9) \ - } Else { \ - Return (0xb) \ - } \ - } \ - Method (_DIS, 0, Serialized) \ - { \ - Or (^^PIR##id, ^^IREN, ^^PIR##id) \ - } \ - } - -MAKE_LINK_DEV(A,1) -MAKE_LINK_DEV(B,2) -MAKE_LINK_DEV(C,3) -MAKE_LINK_DEV(D,4) -MAKE_LINK_DEV(E,5) -MAKE_LINK_DEV(F,6) -MAKE_LINK_DEV(G,7) -MAKE_LINK_DEV(H,8) diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl deleted file mode 100644 index c6c6576..0000000 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - - -#include <intelblocks/itss.h> -#include <intelblocks/pcr.h> -#include <soc/iomap.h> -#include <soc/irq.h> -#include <soc/pcr_ids.h> - -Scope() -{ - // Private Chipset Register(PCR). Memory Mapped through ILB - OperationRegion(PCRR, SystemMemory, P2SB_BAR, 0x01000000) - Field(PCRR, DWordAcc, Lock, Preserve) - { - Offset (0xD03100), // Interrupt Routing Registers - PRTA, 8, - PRTB, 8, - PRTC, 8, - PRTD, 8, - PRTE, 8, - PRTF, 8, - PRTG, 8, - PRTH, 8, - } -} - -Scope (_SB) -{ - #include "pci_irq.asl" - #include "uncore_irq.asl" - #include "iiostack.asl" -} diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl deleted file mode 100644 index 03872e3..0000000 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ /dev/null @@ -1,551 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Uncore devices PCI interrupt routing packages. - * See ACPI spec 6.2.13 _PRT (PCI routing table) for details. - * The mapping fields ae Address, Pin, Source, Source Index. - */ - -#define GEN_PCIE_LEGACY_IRQ() \ - Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ - Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, \ - Package () { 0x0002FFFF, 0x02, LNKC, 0x00 }, \ - Package () { 0x0003FFFF, 0x03, LNKD, 0x00 } - -#define GEN_UNCORE_LEGACY_IRQ(dev) \ - Package () { ##dev, 0x00, LNKA, 0x00 }, \ - Package () { ##dev, 0x01, LNKB, 0x00 }, \ - Package () { ##dev, 0x02, LNKC, 0x00 }, \ - Package () { ##dev, 0x03, LNKD, 0x00 } - -#define GEN_PCIE_IOAPIC_IRQ(irq1, irq2, irq3, irq4) \ - Package () { 0x0000FFFF, 0x00, 0x00, ##irq1 }, \ - Package () { 0x0001FFFF, 0x01, 0x00, ##irq2 }, \ - Package () { 0x0002FFFF, 0x02, 0x00, ##irq3 }, \ - Package () { 0x0003FFFF, 0x03, 0x00, ##irq4 } - -#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ - Package () { ##dev, 0x00, 0x00, ##irq1 }, \ - Package () { ##dev, 0x01, 0x00, ##irq2 }, \ - Package () { ##dev, 0x02, 0x00, ##irq3 }, \ - Package () { ##dev, 0x03, 0x00, ##irq4 } - -// Socket 0, IIOStack 0 device legacy interrupt routing -Name (PR00, Package (0x28) -{ - // [DMI0]: Legacy PCI Express Port 0 - Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, - // [CB0A]: CBDMA - // [CB0E]: CBDMA - Package () { 0x0004FFFF, 0x00, LNKA, 0x00 }, - // [CB0B]: CBDMA - // [CB0F]: CBDMA - Package () { 0x0004FFFF, 0x01, LNKB, 0x00 }, - // [CB0C]: CBDMA - // [CB0G]: CBDMA - Package () { 0x0004FFFF, 0x02, LNKC, 0x00 }, - // [CB0D]: CBDMA - // [CB0H]: CBDMA - Package () { 0x0004FFFF, 0x03, LNKD, 0x00 }, - // Uncore 0 UBOX Device - Package () { 0x0008FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0008FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0008FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0008FFFF, 0x03, LNKD, 0x00 }, - // [DISP]: Display Controller - Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, - // [IHC1]: HECI #1 - // [IHC3]: HECI #3 - Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, - // [IHC2]: HECI #2 - Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, - // [IIDR]: IDE-Redirection (IDE-R) - Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, - // [IMKT]: Keyboard and Text (KT) Redirection - Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, - // [SAT2]: sSATA Host controller 2 on PCH - Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, - // // [XHCI]: xHCI controller 1 on PCH - Package () { 0x0014FFFF, 0x00, LNKA, 0x00 }, - // [OTG0]: USB Device Controller (OTG) on PCH - Package () { 0x0014FFFF, 0x01, LNKB, 0x00 }, - // [TERM]: Thermal Subsystem on PCH - Package () { 0x0014FFFF, 0x02, LNKC, 0x00 }, - // [CAMR]: Camera IO Host Controller on PCH - Package () { 0x0014FFFF, 0x03, LNKD, 0x00 }, - // [HEC1]: HECI #1 on PCH - // [HEC3]: HECI #3 on PCH - Package () { 0x0016FFFF, 0x00, LNKA, 0x00 }, - // [HEC2]: HECI #2 on PCH - Package () { 0x0016FFFF, 0x01, LNKB, 0x00 }, - // [IDER]: ME IDE redirect on PCH - Package () { 0x0016FFFF, 0x02, LNKC, 0x00 }, - // [MEKT]: MEKT on PCH - Package () { 0x0016FFFF, 0x03, LNKD, 0x00 }, - // [SAT1]: SATA controller 1 on PCH - Package () { 0x0017FFFF, 0x00, LNKA, 0x00 }, - // [NAN1]: NAND Cycle Router on PCH - Package () { 0x0018FFFF, 0x00, LNKA, 0x00 }, - // [RP17]: PCIE PCH Root Port #17 - Package () { 0x001BFFFF, 0x00, LNKA, 0x00 }, - // [RP18]: PCIE PCH Root Port #18 - Package () { 0x001BFFFF, 0x01, LNKB, 0x00 }, - // [RP19]: PCIE PCH Root Port #19 - Package () { 0x001BFFFF, 0x02, LNKC, 0x00 }, - // [RP20]: PCIE PCH Root Port #20 - Package () { 0x001BFFFF, 0x03, LNKD, 0x00 }, - // [RP01]: PCIE PCH Root Port #1 - // [RP05]: PCIE PCH Root Port #5 - Package () { 0x001CFFFF, 0x00, LNKA, 0x00 }, - // [RP02]: PCIE PCH Root Port #2 - // [RP06]: PCIE PCH Root Port #6 - Package () { 0x001CFFFF, 0x01, LNKB, 0x00 }, - // [RP03]: PCIE PCH Root Port #3 - // [RP07]: PCIE PCH Root Port #7 - Package () { 0x001CFFFF, 0x02, LNKC, 0x00 }, - // [RP04]: PCIE PCH Root Port #4 - // [RP08]: PCIE PCH Root Port #8 - Package () { 0x001CFFFF, 0x03, LNKD, 0x00 }, - // [RP09]: PCIE PCH Root Port #9 - // [RP13]: PCIE PCH Root Port #13 - Package () { 0x001DFFFF, 0x00, LNKA, 0x00 }, - // [RP10]: PCIE PCH Root Port #10 - // [RP14]: PCIE PCH Root Port #14 - Package () { 0x001DFFFF, 0x01, LNKB, 0x00 }, - // [RP11]: PCIE PCH Root Port #11 - // [RP15]: PCIE PCH Root Port #15 - Package () { 0x001DFFFF, 0x02, LNKC, 0x00 }, - // [RP12]: PCIE PCH Root Port #12 - // [RP16]: PCIE PCH Root Port #16 - Package () { 0x001DFFFF, 0x03, LNKD, 0x00 }, - // [UAR0]: UART #0 on PCH - Package () { 0x001EFFFF, 0x02, LNKC, 0x00 }, - // [UAR1]: UART #1 on PCH - Package () { 0x001EFFFF, 0x03, LNKD, 0x00 }, - // [CAVS]: HD Audio Subsystem Controller on PCH - // [SMBS]: SMBus controller on PCH - // [GBE1]: GbE Controller on PCH - // [NTPK]: Northpeak Controller on PCH - Package () { 0x001FFFFF, 0x00, LNKA, 0x00 }, -}) - -// Socket 0, IIOStack 0 device IOAPIC interrupt routing -Name (AR00, Package (0x28) -{ - // [DMI0]: Legacy PCI Express Port 0 - Package () { 0x0000FFFF, 0x00, 0x00, 0x1F }, - // [CB0A]: CB3DMA - // [CB0E]: CB3DMA - Package () { 0x0004FFFF, 0x00, 0x00, 0x1A }, - // [CB0B]: CB3DMA - // [CB0F]: CB3DMA - Package () { 0x0004FFFF, 0x01, 0x00, 0x1B }, - // [CB0C]: CB3DMA - // [CB0G]: CB3DMA - Package () { 0x0004FFFF, 0x02, 0x00, 0x1A }, - // [CB0D]: CB3DMA - // [CB0H]: CB3DMA - Package () { 0x0004FFFF, 0x03, 0x00, 0x1B }, - // [UBX0]: Uncore 0 UBOX Device - Package () { 0x0008FFFF, 0x00, 0x00, 0x18 }, - Package () { 0x0008FFFF, 0x01, 0x00, 0x1C }, - Package () { 0x0008FFFF, 0x02, 0x00, 0x1D }, - Package () { 0x0008FFFF, 0x03, 0x00, 0x1E }, - // [DISP]: Display Controller - Package () { 0x000FFFFF, 0x00, 0x00, 0x10 }, - // [IHC1]: HECI #1 - // [IHC3]: HECI #3 - Package () { 0x0010FFFF, 0x00, 0x00, 0x10 }, - // [IHC2]: HECI #2 - Package () { 0x0010FFFF, 0x01, 0x00, 0x11 }, - // [IIDR]: IDE-Redirection (IDE-R) - Package () { 0x0010FFFF, 0x02, 0x00, 0x12 }, - // [IMKT]: Keyboard and Text (KT) Redirection - Package () { 0x0010FFFF, 0x03, 0x00, 0x13 }, - // [SAT2]: sSATA Host controller 2 on PCH - Package () { 0x0011FFFF, 0x00, 0x00, 0x10 }, - // [XHCI]: xHCI controller 1 on PCH - Package () { 0x0014FFFF, 0x00, 0x00, 0x10 }, - // [OTG0]: USB Device Controller (OTG) on PCH - Package () { 0x0014FFFF, 0x01, 0x00, 0x11 }, - // [TERM]: Thermal Subsystem on PCH - Package () { 0x0014FFFF, 0x02, 0x00, 0x12 }, - // [CAMR]: Camera IO Host Controller on PCH - Package () { 0x0014FFFF, 0x03, 0x00, 0x13 }, - // [HEC1]: HECI #1 on PCH - // [HEC3]: HECI #3 on PCH - Package () { 0x0016FFFF, 0x00, 0x00, 0x10 }, - // [HEC2]: HECI #2 on PCH - Package () { 0x0016FFFF, 0x01, 0x00, 0x11 }, - // [IDER]: ME IDE redirect on PCH - Package () { 0x0016FFFF, 0x02, 0x00, 0x12 }, - // [MEKT]: MEKT on PCH - Package () { 0x0016FFFF, 0x03, 0x00, 0x13 }, - // [SAT1]: SATA controller 1 on PCH - Package () { 0x0017FFFF, 0x00, 0x00, 0x10 }, - // [NAN1]: NAND Cycle Router on PCH - Package () { 0x0018FFFF, 0x00, 0x00, 0x10 }, - // [RP17]: PCIE PCH Root Port #17 - Package () { 0x001BFFFF, 0x00, 0x00, 0x10 }, - // [RP18]: PCIE PCH Root Port #18 - Package () { 0x001BFFFF, 0x01, 0x00, 0x11 }, - // [RP19]: PCIE PCH Root Port #19 - Package () { 0x001BFFFF, 0x02, 0x00, 0x12 }, - // [RP20]: PCIE PCH Root Port #20 - Package () { 0x001BFFFF, 0x03, 0x00, 0x13 }, - // [RP01]: PCIE PCH Root Port #1 - // [RP05]: PCIE PCH Root Port #5 - Package () { 0x001CFFFF, 0x00, 0x00, 0x10 }, - // [RP02]: PCIE PCH Root Port #2 - // [RP06]: PCIE PCH Root Port #6 - Package () { 0x001CFFFF, 0x01, 0x00, 0x11 }, - // [RP03]: PCIE PCH Root Port #3 - // [RP07]: PCIE PCH Root Port #7 - Package () { 0x001CFFFF, 0x02, 0x00, 0x12 }, - // [RP04]: PCIE PCH Root Port #4 - // [RP08]: PCIE PCH Root Port #8 - Package () { 0x001CFFFF, 0x03, 0x00, 0x13 }, - // [RP09]: PCIE PCH Root Port #9 - // [RP13]: PCIE PCH Root Port #13 - Package () { 0x001DFFFF, 0x00, 0x00, 0x10 }, - // [RP10]: PCIE PCH Root Port #10 - // [RP14]: PCIE PCH Root Port #14 - Package () { 0x001DFFFF, 0x01, 0x00, 0x11 }, - // [RP11]: PCIE PCH Root Port #11 - // [RP15]: PCIE PCH Root Port #15 - Package () { 0x001DFFFF, 0x02, 0x00, 0x12 }, - // [RP12]: PCIE PCH Root Port #12 - // [RP16]: PCIE PCH Root Port #16 - Package () { 0x001DFFFF, 0x03, 0x00, 0x13 }, - // [UAR0]: UART #0 on PCH - Package () { 0x001EFFFF, 0x02, 0x00, 0x16 }, - // [UAR1]: UART #1 on PCH - Package () { 0x001EFFFF, 0x03, 0x00, 0x17 }, - // [CAVS]: HD Audio Subsystem Controller on PCH - // [SMBS]: SMBus controller on PCH - // [GBE1]: GbE Controller on PCH - // [NTPK]: Northpeak Controller on PCH - Package () { 0x001FFFFF, 0x00, 0x00, 0x10 }, -}) - -// Socket 0, IIOStack 1 device legacy interrupt routing -Name (PR10, Package (0x40) -{ - // PCI Express Port 1A-1D - GEN_PCIE_LEGACY_IRQ(), - - // Uncore CHAUTIL Devices - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - - // Uncore CHASAD Devices - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), - - // Uncore CMSCHA Devices - GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), - - // Uncore CHASADALL Device - GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), - - // Uncore PCUCR Device - GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), - - // Uncore VCUCR Device - GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) -}) - -// Socket 0, IIOStack 1 device IOAPIC interrupt routing -Name (AR10, Package (0x40) -{ - // PCI Express Port A-D - GEN_PCIE_IOAPIC_IRQ(0x27,0x21,0x22,0x23), - - // Uncore CHAUTIL Devices - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore CHASAD Devices - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore CMSCHA Devices - GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore CHASADALL Device - GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore PCUCR Device - GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore VCUCR Device - GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x20, 0x24, 0x25, 0x26) -}) - -// Socket 0, IIOStack 2 device legacy interrupt routing -Name (PR20, Package (0x24) -{ - // PCI Express Port A-D on PC02 - GEN_PCIE_LEGACY_IRQ(), - - // Uncore M2MEM Devices - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - - // Uncore MCMAIN Device - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - - // Uncore MCDECS2 Device - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - - // Uncore MCMAIN Device - GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), - - // Uncore MCDECS Device - GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), - - // Uncore Unicast MC0 DDRIO0 Device - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - - // Uncore Unicast MC1 DDRIO0 Device - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 0, IIOStack 2 device IOAPIC interrupt routing -Name (AR20, Package (0x24) -{ - // PCI Express Port A-D on PC02 - GEN_PCIE_IOAPIC_IRQ(0x2F,0x29,0x2A,0x2B), - - // Uncore M2MEM Devices - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x28, 0x2C, 0x2D, 0x2E), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCMAIN Device - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCDECS2 Device - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCMAIN Device - GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCDECS Device - GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore Unicast MC0 DDRIO0 Device - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore Unicast MC1 DDRIO0 Device - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x28, 0x2C, 0x2D, 0x2E) -}) - -// Socket 0, IIOStack 3 device legacy interrupt routing -Name (PR28, Package (0x20) -{ - // PCI Express Port 3 on PC03 - GEN_PCIE_LEGACY_IRQ(), - - // KTI Devices - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - - // M3K Device - GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), - - // M2U Device - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - - // M2D Device - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - - // M20 Device - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 0, IIOStack 3 device IOAPIC interrupt routing -Name (AR28, Package (0x20) -{ - // PCI Express Port A-D on PC03 - GEN_PCIE_IOAPIC_IRQ(0x37,0x31,0x32,0x33), - - // KTI Devices - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x30, 0x34, 0x35, 0x36), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x30, 0x34, 0x35, 0x36), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x30, 0x34, 0x35, 0x36), - - // M3K Device - GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x30, 0x34, 0x35, 0x36), - - // M2U Device - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x30, 0x34, 0x35, 0x36), - - // M2D Device - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x30, 0x34, 0x35, 0x36), - - // M20 Device - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x30, 0x34, 0x35, 0x36) -}) - -// Socket 1, IIOStack 0 device legacy interrupt routing -Name (PR40, Package (0x09) -{ - // DMI - Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, - - // CBDMA - GEN_UNCORE_LEGACY_IRQ(0x0004FFFF), - - // Ubox - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF) -}) - -// Socket 1, IIOStack 0 device IOAPIC interrupt routing -Name (AR40, Package (0x09) -{ - // DMI - Package () { 0x0000FFFF, 0x00, 0x00, 0x4F }, - - // CBDMA - GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B), - - // Ubox - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x48, 0x4C, 0x4D, 0x4E), -}) - -// Socket 1, IIOStack 1 device legacy interrupt routing -Name (PR50, Package (0x40) -{ - // PCI Express Port - GEN_PCIE_LEGACY_IRQ(), - - // CHA Devices - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), - GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), - - // PCU Devices - GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) -}) - -// Socket 1, IIOStack 1 device IOAPIC interrupt routing -Name (AR50, Package (0x40) -{ - // PCI Express Port A-D - GEN_PCIE_IOAPIC_IRQ(0x57,0x51,0x52,0x53), - - // CHA Devices - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x50, 0x54, 0x55, 0x56), - - // PCU Devices - GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x50, 0x54, 0x55, 0x56) -}) - -// Socket 1, IIOStack 2 device legacy interrupt routing -Name (PR60, Package (0x24) -{ - // PCI Express Port - GEN_PCIE_LEGACY_IRQ(), - - // Integrated Memory Controller - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - - // Uncore Devices - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 1, IIOStack 2 device IOAPIC interrupt routing -Name (AR60, Package (0x24) -{ - // PCI Express Port A-D - GEN_PCIE_IOAPIC_IRQ(0x5F,0x59,0x5A,0x5B), - - // Integrated Memory Controller - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x58, 0x5C, 0x5D, 0x5E), - - // Uncore Devices - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x58, 0x5C, 0x5D, 0x5E) -}) - -// Socket 1, IIOStack 3 device legacy interrupt routing -Name (PR68, Package (0x20) -{ - // PCI Express Port - GEN_PCIE_LEGACY_IRQ(), - - // Uncore Devices - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 1, IIOStack 3 device legacy interrupt routing -Name (AR68, Package (0x20) -{ - // PCI Express Port A-D - GEN_PCIE_IOAPIC_IRQ(0x67,0x61,0x62,0x63), - - // Uncore Devices - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x60, 0x64, 0x65, 0x66) -})