[coreboot-gerrit] Change in coreboot[master]: nb/intel/fsp_sandy: Use common init_igd_opregion method

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19906 )

Change subject: nb/intel/fsp_sandy: Use common init_igd_opregion method
......................................................................

nb/intel/fsp_sandy: Use common init_igd_opregion method

Use common init_igd_opregion method.

Change-Id: Ie70a49fd532b7ad7679dc558cc4a019a273a0602
Signed-off-by: Patrick Rudolph 
---
M src/northbridge/intel/fsp_sandybridge/Kconfig
M src/northbridge/intel/fsp_sandybridge/acpi.c
M src/northbridge/intel/fsp_sandybridge/gma.c
M src/northbridge/intel/fsp_sandybridge/northbridge.h
4 files changed, 40 insertions(+), 159 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/19906/1

diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig
index 89326b4..5446ba3 100644
--- a/src/northbridge/intel/fsp_sandybridge/Kconfig
+++ b/src/northbridge/intel/fsp_sandybridge/Kconfig
@@ -18,11 +18,13 @@
    bool
    select CPU_INTEL_FSP_MODEL_206AX
    select INTEL_GMA_ACPI
+	select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION

config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE
    bool
    select CPU_INTEL_FSP_MODEL_306AX
    select INTEL_GMA_ACPI
+	select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION

if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE

diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c
index a30cb7a..28df4a5 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi.c
+++ b/src/northbridge/intel/fsp_sandybridge/acpi.c
@@ -16,18 +16,10 @@
  */

#include <types.h>
-#include <string.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/acpi.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <drivers/intel/gma/i915.h>
-#include <arch/acpigen.h>
 #include "northbridge.h"
-#include <cbmem.h>
-#include <drivers/intel/gma/intel_bios.h>

unsigned long acpi_fill_mcfg(unsigned long current)
 {
@@ -72,138 +64,4 @@
    		pciexbar, 0x0, 0x0, max_buses - 1);

return current;
-}
-
-static void *get_intel_vbios(void)
-{
-	/* This should probably be looking at CBFS or we should always
-	 * deploy the VBIOS on Intel systems, even if we don't run it
-	 * in coreboot (e.g. SeaBIOS only scenarios).
-	 */
-	u8 *vbios = (u8 *)0xc0000;
-
-	optionrom_header_t *oprom = (optionrom_header_t *)vbios;
-	optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
-						oprom->pcir_offset);
-
-
-	printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
-		oprom->signature, pcir->vendor, pcir->classcode[0],
-		pcir->classcode[1], pcir->classcode[2]);
-
-
-	if ((oprom->signature == OPROM_SIGNATURE) &&
-		(pcir->vendor == PCI_VENDOR_ID_INTEL) &&
-		(pcir->classcode[0] == 0x00) &&
-		(pcir->classcode[1] == 0x00) &&
-		(pcir->classcode[2] == 0x03))
-		return (void *)vbios;
-
-	return NULL;
-}
-
-static int init_opregion_vbt(igd_opregion_t *opregion)
-{
-	void *vbios;
-	vbios = get_intel_vbios();
-	if (!vbios) {
-		printk(BIOS_DEBUG, "VBIOS not found.\n");
-		return 1;
-	}
-
-	printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
-	optionrom_header_t *oprom = (optionrom_header_t *)vbios;
-	optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
-						oprom->vbt_offset);
-
-	if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
-		printk(BIOS_DEBUG, "VBT not found!\n");
-		return 1;
-	}
-
-	memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
-	memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
-						vbt->hdr_vbt_size : 7168);
-
-	return 0;
-}
-
-
-/* Initialize IGD OpRegion, called from ACPI code */
-int init_igd_opregion(igd_opregion_t *opregion)
-{
-	device_t igd;
-	u16 reg16;
-
-	memset((void *)opregion, 0, sizeof(igd_opregion_t));
-
-	// FIXME if IGD is disabled, we should exit here.
-
-	memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
-		sizeof(opregion->header.signature));
-
-	/* 8kb */
-	opregion->header.size = sizeof(igd_opregion_t) / 1024;
-	opregion->header.version = IGD_OPREGION_VERSION;
-
-	// FIXME We just assume we're mobile for now
-	opregion->header.mailboxes = MAILBOXES_MOBILE;
-
-	// TODO Initialize Mailbox 1
-
-	// TODO Initialize Mailbox 3
-	opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
-	opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
-	opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
-	opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
-	opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
-	opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
-	opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
-	opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
-	opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
-	opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
-	opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
-	opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
-	opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
-	opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
-	opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
-
-	init_opregion_vbt(opregion);
-
-	/* TODO This needs to happen in S3 resume, too.
-	 * Maybe it should move to the finalize handler
-	 */
-	igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
-
-	pci_write_config32(igd, ASLS, (u32)opregion);
-	reg16 = pci_read_config16(igd, SWSCI);
-	reg16 &= ~(1 << 0);
-	reg16 |= (1 << 15);
-	pci_write_config16(igd, SWSCI, reg16);
-
-	/* clear dmisci status */
-	reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
-	reg16 |= DMISCI_STS; // reference code does an &=
-	outw(DEFAULT_PMBASE + TCO1_STS, reg16);
-
-	/* clear acpi tco status */
-	outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
-
-	/* enable acpi tco scis */
-	reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
-	reg16 |= TCOSCI_EN;
-	outw(DEFAULT_PMBASE + GPE0_EN, reg16);
-
-	return 0;
-}
-
-void *igd_make_opregion(void)
-{
-	igd_opregion_t *opregion;
-
-	printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
-	opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion));
-	if (opregion)
-		init_igd_opregion(opregion);
-	return opregion;
 }
diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c
index 0034b06..8e2d968 100644
--- a/src/northbridge/intel/fsp_sandybridge/gma.c
+++ b/src/northbridge/intel/fsp_sandybridge/gma.c
@@ -20,6 +20,9 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <southbridge/intel/fsp_bd82x6x/nvs.h>
+#include <northbridge/intel/common/gma_opregion.h>
+#include <drivers/intel/gma/intel_bios.h>
+
 #include <cbmem.h>

#include "chip.h"
@@ -82,27 +85,50 @@
    drivers_intel_gma_displays_ssdt_generate(gfx);
 }

+/* Enable SCI to ACPI _GPE._L06 */
+static void gma_enable_swsci(void)
+{
+	u16 reg16;
+
+	/* clear DMISCI status */
+	reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
+	reg16 &= DMISCI_STS;
+	outw(DEFAULT_PMBASE + TCO1_STS, reg16);
+
+	/* clear acpi tco status */
+	outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
+
+	/* enable acpi tco scis */
+	reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
+	reg16 |= TCOSCI_EN;
+	outw(DEFAULT_PMBASE + GPE0_EN, reg16);
+}
+
 static unsigned long
 gma_write_acpi_tables(struct device *const dev,
    	      unsigned long current,
    	      struct acpi_rsdp *const rsdp)
 {
-	igd_opregion_t *opregion;
+	igd_opregion_t *opregion = (igd_opregion_t *)current;
    global_nvs_t *gnvs;

-	// FIXME: Replace by common VBT implementation writing to current
-	opregion = igd_make_opregion();
-	if (opregion) {
-		/* GNVS has been already set up */
-		gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-		if (gnvs) {
-			/* IGD OpRegion Base Address */
-			gnvs->aslb = (u32)(uintptr_t)opregion;
-		} else {
-			printk(BIOS_ERR, "Error: GNVS table not found.\n");
-		}
+	if (init_igd_opregion(opregion) != CB_SUCCESS)
+		return current;
+
+	current += sizeof(igd_opregion_t);
+
+	/* GNVS has been already set up */
+	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+	if (gnvs) {
+		/* IGD OpRegion Base Address */
+		gnvs->aslb = (u32)(uintptr_t)opregion;
+	} else {
+		printk(BIOS_ERR, "Error: GNVS table not found.\n");
    }

+	gma_enable_swsci();
+
+	current = acpi_align_current(current);
    return current;
 }

diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h
index 0be01cc..c0194f2 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.h
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h
@@ -215,11 +215,6 @@
 void report_platform_info(void);
 #endif /* !__SMM__ */

-#if !defined(__PRE_RAM__)
-#include <drivers/intel/gma/opregion.h>
-int init_igd_opregion(igd_opregion_t *igd_opregion);
-#endif
-
 #endif
 #endif
 #endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */