[coreboot-gerrit] [XS] Change in coreboot[main]: intel/common/rtd3: Allow emitting PSD0 Method for CPU Root Ports

[Subrata Banik (Code Review)]

Attention is currently required from: Sean Rhodes.

Subrata Banik has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85696?usp=email )

Change subject: intel/common/rtd3: Allow emitting PSD0 Method for CPU Root Ports
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Patch Set 5:

(1 comment)

File src/soc/intel/common/block/pcie/rtd3/rtd3.c:

https://review.coreboot.org/c/coreboot/+/85696/comment/262ee399_fcca289e?usp... :
PS5, Line 437: 	if (rp_type != PCIE_RP_PCH) {
earlier code was applicable for both CPU RPs as well but your patch looks like limiting it to only unknown RPs ?
```
enum pcie_rp_type {
    PCIE_RP_UNKNOWN,
    PCIE_RP_CPU,
    PCIE_RP_PCH,
};
```

is there any doc to refer is `ext_pm_support` support also applies for CPU RPs ? not sure why it had been limited initially.