Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42800 )
Change subject: mb/google/zork: Disable unsupported SOC usb ports ......................................................................
mb/google/zork: Disable unsupported SOC usb ports
Disable USB ports that are not supported by the SOC. Handles Dali, Picasso and Pollock.
BUG=b:158096224 TEST=Boot Picasso Ezkinil, observe ports disabled
Change-Id: Ie37e2ac6a3a26edf77823193e592310eb10b9f9c Signed-off-by: Rob Barnes robbarnes@google.com --- M src/soc/amd/picasso/chip.c 1 file changed, 30 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/42800/1
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index c510efe..fb5fb98 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -9,6 +9,7 @@ #include <soc/data_fabric.h> #include <soc/iomap.h> #include <soc/pci_devs.h> +#include <soc/soc_util.h> #include <soc/southbridge.h> #include "chip.h" #include <fsp/api.h> @@ -127,12 +128,40 @@ } }
+/** + * Disables USB ports not supported on the SOC variant. + */ +static void disable_unsupported_usb_ports(void) { + struct device *bus_a, *xhci0, *xhci1, *hub, *port; + + bus_a = pcidev_path_on_root(PCI_DEVFN(8, 1)); + xhci0 = pcidev_path_behind(bus_a->link_list, PCI_DEVFN(0,3)); + hub = xhci0->link_list->children; + port = NULL; + while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { + unsigned int port_id = port->path.usb.port_id; + /* Picasso SOC only has 4 USB ports on XHCI0 */ + if(!soc_is_raven2() && port->enabled && port_id > 3) { + printk(BIOS_INFO,"Disabling XHCI0 USB port %s because it is not supported on this SOC\n", dev_path(port)); + dev_set_enabled(port, 0); + } + } + + xhci1 = pcidev_path_behind(bus_a->link_list, PCI_DEVFN(0,4)); + hub = xhci1->link_list->children; + /* Dali and Pollock do not have USB ports on XHCI1 */ + if(soc_is_raven2() && hub->enabled) { + printk(BIOS_INFO,"Disabling XHCI1 USB hub because it is not supported on this SOC\n"); + disable_children(hub->bus); + } +} + static void soc_init(void *chip_info) { default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
fsp_silicon_init(acpi_is_wakeup_s3()); - + disable_unsupported_usb_ports(); data_fabric_set_mmio_np(); southbridge_init(chip_info); }