Attention is currently required from: Sean Rhodes, Tarun Tuli, Subrata Banik, Lean Sheng Tan, Felix Held.
Hello build bot (Jenkins), Sean Rhodes, Tarun Tuli, Subrata Banik, Lean Sheng Tan, Felix Held,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/73901
to review the following change.
Change subject: Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol" ......................................................................
Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol"
This reverts commit fd4ad29f1824ad5d8df67f3e30d3908d24cbd8a4.
Reason for revert: TBD; other revert depends on it
Change-Id: I5ed5e3e267032d62d65aef7fb246a075dccc9cf6 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/acpi/tcss.asl M src/soc/intel/alderlake/acpi/tcss_dma.asl M src/soc/intel/alderlake/acpi/tcss_pcierp.asl M src/soc/intel/alderlake/acpi/tcss_xhci.asl M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/tigerlake/acpi/tcss_dma.asl M src/soc/intel/tigerlake/acpi/tcss_pcierp.asl M src/soc/intel/tigerlake/acpi/tcss_xhci.asl 10 files changed, 60 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/73901/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a8c9aeb..dd6bb22 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -328,6 +328,12 @@ int default 8
+config SOC_INTEL_ALDERLAKE_S3 + bool + default n + help + Select if using S3 instead of S0ix to disable D3Cold. + config ENABLE_SATA_TEST_MODE bool "Enable test mode for SATA margining" default n diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 5c95997..1f626fc 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -583,7 +583,7 @@ } }
-#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -654,7 +654,7 @@ STAT = 0 } } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3
/* * TCSS xHCI device diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index ca47bd0..1483c0b 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -28,16 +28,16 @@
Method (_S0W, 0x0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Return (0x04) #else Return (0x03) -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 }
Method (_PR0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If (DUID == 0) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -49,12 +49,12 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 }
Method (_PR3) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If (DUID == 0) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -66,7 +66,7 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 }
/* diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index 6dbde46..4f1eec5 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -247,16 +247,16 @@
Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Return (0x4) #else Return (0x3) -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 }
Method (_PR0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -268,12 +268,12 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 }
Method (_PR3) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -285,7 +285,7 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 }
/* diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl index ddc5a66..c0dc141 100644 --- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl @@ -30,11 +30,11 @@
Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Return (0x4) #else Return (0x3) -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3 }
/* @@ -43,7 +43,7 @@ */ Name (SD3C, 0)
-#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Method (_PR0) { Return (Package () { _SB.PCI0.D3C }) @@ -53,7 +53,7 @@ { Return (Package () { _SB.PCI0.D3C }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_ALDERLAKE_S3
/* * XHCI controller _DSM method diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index d4b16c0..788ee51 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -206,6 +206,12 @@ int default 6
+config SOC_INTEL_TIGERLAKE_S3 + bool + default n + help + Select if using S3 instead of S0ix to disable D3Cold + config SOC_INTEL_UART_DEV_MAX int default 3 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 98337a3..be9d306 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -676,7 +676,7 @@ } }
-#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -787,7 +787,7 @@ STAT = 0 } } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3
/* * TCSS xHCI device diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index bbb0b6a..3c19ef6 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -27,11 +27,11 @@
Method (_S0W, 0x0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) Return (0x04) #else Return (0x03) -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 }
/* @@ -40,7 +40,7 @@ */ Method (_PR0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) If (DUID == 0) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -52,12 +52,12 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 }
Method (_PR3) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) If (DUID == 0) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -69,7 +69,7 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 }
/* diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index a8e19ed..fda58e7 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -247,7 +247,7 @@
Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) Return (0x4) #else Return (0x3) @@ -256,7 +256,7 @@
Method (_PR0) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -268,12 +268,12 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 }
Method (_PR3) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -285,7 +285,7 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 }
/* diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl index ddc5a66..a3b8c8f 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl @@ -30,11 +30,11 @@
Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) Return (0x4) #else Return (0x3) -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3 }
/* @@ -43,7 +43,7 @@ */ Name (SD3C, 0)
-#if CONFIG(D3COLD_SUPPORT) +#if !CONFIG(SOC_INTEL_TIGERLAKE_S3) Method (_PR0) { Return (Package () { _SB.PCI0.D3C }) @@ -53,7 +53,7 @@ { Return (Package () { _SB.PCI0.D3C }) } -#endif // D3COLD_SUPPORT +#endif // SOC_INTEL_TIGERLAKE_S3
/* * XHCI controller _DSM method