Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 )
Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
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Patch Set 8: Code-Review-1
FSP MR2 does a check for ACPI mode and change the device mode. Supplying incorrect configuration will be corrected by FSP, but to be futher proof supply correct configuration to FSP.
I can't say that I understand this yet. You are saying FSP
allows a value of 2 (PCH_ACPI_MODE). But then you say FSP
would be correcting incorrect configuration, which translates
to me as it reads the hardware state and ignores the diffe-
rence between a 1 and a 2.
And about being future proof. That's generally a good idea,
but how can we anticipate the future here? How can we tell
that if FSP is being corrected, if the code will be made to
match the header file or the other way around?
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