Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34662 )
Change subject: Documentation/binaries: Add AMD FSP documentation ......................................................................
Documentation/binaries: Add AMD FSP documentation
Create a document explaining, at a high level, the differences between Intel's FSP and the one developed by AMD.
BUG=none. TEST=none.
Change-Id: I59a5d34df93cd0ff647e2ccfdbf8700b4df00a59 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- A Documentation/binaries/AMD_FSP_family_17h.md A Documentation/binaries/index.md 2 files changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34662/1
diff --git a/Documentation/binaries/AMD_FSP_family_17h.md b/Documentation/binaries/AMD_FSP_family_17h.md new file mode 100644 index 0000000..b46beb3 --- /dev/null +++ b/Documentation/binaries/AMD_FSP_family_17h.md @@ -0,0 +1,41 @@ +# FSP implementation differences between Intel and AMD + +## Introduction +Starting with family 17h, AMD is developing an "_As Close As Possible_" FSP +binary. However, some premisses are different for family 17h and beyond, +making it necessary to have some FSP implementation differences. Some other +implementation differences were more of an engineering decision. + +The family 17h deviation from older AMD and Intel CPU/SOC are: +* The memory is initialized by the PSP (similar to Intel's ME) ARM. +* There's _**no support**_ for cache as RAM. +* Reset vector is not the old 0xFFFFFFF0. + +This document is a "work in progress", documenting the differences at a +high level. This document will be updated as more information becomes +available. + +## Differences caused by differences in premisses +1. **No FSP-T** +Because family 17h does not support CAR, there's no FSP-T. +2. **FSP-M only reports memory** +Because memory is inittialized by the PSP, FSP-M only reports the final +memory configuration. +3. **FSP-M is loaded to DRAM** +PSP can be made to load a section of the flash into RAM before releasing +the reset, thus FSP-M can be made to run directly from memory. +4. **FSP-M can be made position independent** +Because it's loaded to memory and does not uses CAR, FSP-M can be made PIC +(Position Independent Code). + +## Differences by engineering decision +1. **Memory fragmentation** +Though FSP still fragments memory, it has added control for flexibility +of where the chunks will reside. +2. **UPD interface** +UPD interface uses native intergers and don't need to be packed by compiler. +3. **UPD with no UEFI dependencies** +UPD interface can be made C99 or C11 compatible with no hard dependencies +to UEFI. +4. **Platform specific code** +Similar to AGESA, FSP will make call back to platform specific code. diff --git a/Documentation/binaries/index.md b/Documentation/binaries/index.md new file mode 100644 index 0000000..9093bf7 --- /dev/null +++ b/Documentation/binaries/index.md @@ -0,0 +1,8 @@ +# binaries-specific documentation + +This section contains documentation about any binary used by coreboot + +## Video + +## Platform initialization +- [AMD FSP](AMD_FSP_family_17h.md)