[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31368 )

Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
......................................................................

soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11

According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1
should be clear to prevent unexpected I2C behaviors.

BUG=b:124269499
TEST=boot on nami and check bit 25 TOL_1V8 is clear

Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c
Signed-off-by: Kane Chen 
Reviewed-on: https://review.coreboot.org/c/31368
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
M src/soc/intel/skylake/gpio.c
3 files changed, 34 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index 6390315..d77e052 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -273,6 +273,9 @@
    	soc_pad_conf &= mask[i];
    	soc_pad_conf |= pad_conf & ~mask[i];

+		/* Patch GPIO settings for SoC specifically */
+		soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf);
+
    	if (IS_ENABLED(CONFIG_DEBUG_GPIO))
    		printk(BIOS_DEBUG,
    		"gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
@@ -571,3 +574,9 @@
    const struct pad_community *comm = gpio_get_community(gpio_num);
    return comm->acpi_path;
 }
+
+uint32_t __weak soc_gpio_pad_config_fixup(const struct pad_config *cfg,
+						int dw_reg, uint32_t reg_val)
+{
+	return reg_val;
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index c389ec4..11a03d0 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -197,5 +197,15 @@
  */
 uint8_t gpio_get_pad_portid(const gpio_t pad);

+/*
+ * Function to patch GPIO settings for SoC specifically
+ *  cfg = pad config contains pad number and reg value.
+ *  dw_reg = pad config dword number.
+ *  reg_val = the reg value need to be patched.
+ * Returns gpio setting patched for SoC specifically
+ */
+uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg,
+						int dw_reg, uint32_t reg_val);
+
 #endif
 #endif /* _SOC_INTELBLOCKS_GPIO_H_ */
diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index f67d4a3..4da705d 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -168,3 +168,18 @@
    *num = ARRAY_SIZE(routes);
    return routes;
 }
+
+uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg,
+					int dw_reg, uint32_t reg_val)
+{
+	if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))
+		return reg_val;
+	/*
+	 * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4
+	 * ~ GPP_F11.
+	 */
+	if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && dw_reg == 1)
+		reg_val = reg_val & ~(PAD_CFG1_TOL_1V8);
+	return reg_val;
+
+}