[coreboot-gerrit] Change in ...coreboot[master]: drivers/intel/fsp1_1: Adjust postcar MTRRs

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33927 )

Change subject: drivers/intel/fsp1_1: Adjust postcar MTRRs
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/33927/1/src/drivers/intel/fsp1_1/car.c 
File src/drivers/intel/fsp1_1/car.c:

https://review.coreboot.org/#/c/33927/1/src/drivers/intel/fsp1_1/car.c@47 
PS1, Line 47: 	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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