Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46418 )
Change subject: mb/intel/adlrvp: Fix SSD detection issue on ADL RVP ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/46418/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46418/1/src/mainboard/intel/adlrvp/... PS1, Line 44: # Enable PCH PCIE RP 5 using CLK 2 : register "PcieRpEnable[4]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcUsage[2]" = "0x4" These PCIe clock source and clock request settings are a bit confusing. Let's suppose that I want to enable RP X+1 with Clock Source Y and Clock Request Z:
# Enable RP X+1 register "PcieRpEnable[X]" = "1"
# RP X+1 uses Clock Source Y register "PcieClkSrcUsage[Y]" = "X"
# Clock Source Y goes with Clock Request Z register "PcieClkSrcClkReq[Y]" = "Z"
Am I understanding this correctly?