Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36627 )
Change subject: soc/intel/icelake: Move pch_early_init from bootblock to romstage ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36627/2/src/soc/intel/icelake/romst... File src/soc/intel/icelake/romstage/pch.c:
https://review.coreboot.org/c/coreboot/+/36627/2/src/soc/intel/icelake/romst... PS2, Line 85: pmc_gpe_init
How are TPM interrupts working with this change? I would not expect the interrupt status to update a […]
TPM is working. here is the log with this changes
coreboot-4.10-1405-g7bf7601-dirty Wed Nov 6 05:10:16 UTC 2019 verstage starting (log level: 8)... Probing TPM: . done! TPM ready after 3 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.10/29d77172 RW_B:0.3.10/cr50_v1.9308_87_mp.104-7508e4e Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded Chrome EC: UHEPI supported Phase 1 FMAP: Found "FLASH" version 1.1 at 1c04000. FMAP: base = fe000000 size = 2000000 #areas = 31 FMAP: area GBB found @ 1c05000 (978944 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ 1c05000 (978944 bytes) VB2:vb2_report_dev_firmware() This is developer signed firmware FMAP: area VBLOCK_A found @ 1400000 (65536 bytes) FMAP: area VBLOCK_A found @ 1400000 (65536 bytes) VB2:vb2_verify_keyblock() Checking key block signature... FMAP: area VBLOCK_A found @ 1400000 (65536 bytes) FMAP: area VBLOCK_A found @ 1400000 (65536 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. Phase 4 FMAP: area FW_MAIN_A found @ 1410000 (2883520 bytes) VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW Saving vboot hash. Saving nvdata Saving secdata tlcl_extend: response is 0 tlcl_extend: response is 0 Slot A is selected CBFS: 'VBOOT' located CBFS at [1410000:153d580) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset ff80 size 12b2c
https://review.coreboot.org/c/coreboot/+/36627/2/src/soc/intel/icelake/romst... PS2, Line 87: enable_rtc_upper_bank
Probably because it lives in lower bank?
might be the case. but i have moved it to bootblock now