Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )
Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri
Sure, I'll create partnerbug implemenation for TcssAuxOri and TcssHslOri and start working. […]
Done
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... PS3, Line 141: memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, : sizeof(config->IomTypeCPortPadCfg));
Yes. it's doable but takes time as the register info for assign GPIO is not available EDS yet. […]
Done