build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45448 )
Change subject: nb/intel/gm45: Add more DMIBAR/EPBAR registers ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/45448/4/src/northbridge/intel/gm45/... File src/northbridge/intel/gm45/pcie.c:
https://review.coreboot.org/c/coreboot/+/45448/4/src/northbridge/intel/gm45/... PS4, Line 35: while ((EPBAR8(EPVC1RSTS) & 1) != 0); trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/45448/4/src/northbridge/intel/gm45/... PS4, Line 40: while ((EPBAR8(EPVC1RSTS) & 2) != 0); trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/45448/4/src/northbridge/intel/gm45/... PS4, Line 58: while ((DMIBAR8(DMIVC1RSTS) & VC1NP) != 0); trailing statements should be on next line