EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38885 )
Change subject: mb/google/drallion: correct USB3 OC pin error ......................................................................
mb/google/drallion: correct USB3 OC pin error
USB3 OC pin was configured wrong pin. Follow HW circuit to set it.
BUG=b:147869924 TEST=USB function works well
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/38885/1
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 06d3e5d..92f3fb9 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -154,9 +154,9 @@ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY"