[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Enable PMC support

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42289 )

Change subject: soc/intel/xeon_sp: Enable PMC support
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Patch Set 3: Code-Review+1

(2 comments)

https://review.coreboot.org/c/coreboot/+/42289/3/src/soc/intel/xeon_sp/inclu... 
File src/soc/intel/xeon_sp/include/soc/pm.h:

https://review.coreboot.org/c/coreboot/+/42289/3/src/soc/intel/xeon_sp/inclu... 
PS3, Line 13: #define PM1_STS			0x00
> For the xeon_sp command header file changes, please make sure they are same for SKX-SP and CPX-SP.

These registers are located in the PCH, which is Lewisburg in both cases.

https://review.coreboot.org/c/coreboot/+/42289/3/src/soc/intel/xeon_sp/pmuti... 
File src/soc/intel/xeon_sp/pmutil.c:

https://review.coreboot.org/c/coreboot/+/42289/3/src/soc/intel/xeon_sp/pmuti... 
PS3, Line 119: PCH_DEV_PMC
Why not use `PCH_DEV_PMC` in the two places `dev` is used?