Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34914 )
Change subject: soc/amd/common: Add AcpiMmio access for SMBus PCI device ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34914/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34914/5//COMMIT_MSG@7 PS5, Line 7: SMBus I'm starting to believe this commit message is misleading, as there is already SMBus access through MMIO. Also, much more then ACPI is accessed through these 256 MMIO registers... as I mentioned on another patch, USB legacy registers are also accessed. And I believe you mentioned UART can also be accessed. Please change the title.
https://review.coreboot.org/c/coreboot/+/34914/5//COMMIT_MSG@9 PS5, Line 9: PCI Which device/function?