Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33193 )
Change subject: soc/intel/{cml, whl}: Add option to skip HECI disable in SMM ......................................................................
soc/intel/{cml, whl}: Add option to skip HECI disable in SMM
This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable.
User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated UPD.
Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig to make HECI disable and WHL/CML has to rely on FSP to make HECI disable.
Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/smihandler.c 5 files changed, 12 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 76906b2..dac3522 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -107,6 +107,7 @@ select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select FSP_T_XIP if FSP_CAR + select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 9af2917..e8f0d17 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -88,7 +88,7 @@
config = dev->chip_info;
- if (config->HeciEnabled == 0) + if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); }
diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index a58c631..ab5ee03 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -23,3 +23,11 @@ Time in milliseconds that SLP_SMI for S5 waits for before enabling sleep. This is required to avoid any race between SLP_SMI and PWRBTN SMI. + +config HECI_DISABLE_USING_SMM + bool + depends on SOC_INTEL_COMMON_BLOCK_SMM + default n + help + HECI disable using SMM. Select this option to make HECI disable + using SMM mode, independent of dedicated UPD to perform HECI disable. diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 052e37d..f0b2918 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -62,6 +62,7 @@ select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO + select HECI_DISABLE_USING_SMM
config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 5c00b63..5fb2480 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -86,7 +86,7 @@
config = dev->chip_info;
- if (config->HeciEnabled == 0) + if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); }