Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34754 )
Change subject: soc/intel/cannonlake: Add provision to skip postcar and load ramstage ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34754/2/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/34754/2/src/soc/intel/cannonlake/ro... PS2, Line 143: set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT); Well the stack frame created for postcar would be exactly want you want to apply prior to run_ramstage() call, isn't it? You probably could replay those MTRRs, just need to keep in mind that you cannot do cache-disable / invd in the sequence since active stack is in CAR?
MTRR manipulations are maybe over-cautios in IA manuals. If you make the sequence right (clear VALID, program new mask and size, set VALID) maybe you can even just overwrite MTRR that covers CAR region. The sensitive cache-lines were allocated with no-evict so will they ever be evicted without explicit invd command?