Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39460 )
Change subject: mainboard: Set Tiger Lake platforms to have retimer config Aux orientation ......................................................................
mainboard: Set Tiger Lake platforms to have retimer config Aux orientation
Since the Type-C ports on all the Tiger Lake platforms have retimers set the TcssAuxOri UPD to 0 in order for the SoC to not misconfigure the ports. Volteer will need some additional changes after this is implemented to account for ports that do not have a retimer.
BUG=b:145943811 BRANCH=none TEST=Boot to OS and check TypeC port1 Display, Connecting type-c display should work regardless of type-c cable orientation.
Change-Id: I29eb0513299126ad8d1ee11ded2c771f28ad13f3 Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 3 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/39460/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index a65e5f1..0352b62 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -112,6 +112,7 @@
# TCSS USB3 register "TcssXhciEn" = "1" + register "TcssAuxOri" = "0"
# DP port register "DdiPortAConfig" = "1" # eDP diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4492acb..11a2883 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -95,6 +95,9 @@ [PchSerialIoIndexUART2] = PchSerialIoPci, }"
+ # TCSS USB3 + register "TcssAuxOri" = "0" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 643db36..1fc1b62 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -91,6 +91,9 @@ [PchSerialIoIndexUART2] = PchSerialIoPci, }"
+ # TCSS USB3 + register "TcssAuxOri" = "0" + #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0"