[coreboot-gerrit] Change in ...coreboot[master]: siemens/mc_apl2: Change SERIRQ mode

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31138

Change subject: siemens/mc_apl2: Change SERIRQ mode
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siemens/mc_apl2: Change SERIRQ mode

Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected.
By removing this entry from devicetree, the default value (quiet mode)
is used.

Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
1 file changed, 0 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/31138/1

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
index e54444a..c362e6c 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
@@ -5,7 +5,6 @@
    end

register "sci_irq" = "SCIS_IRQ10"
-	register "serirq_mode" = "SERIRQ_CONTINUOUS"

# Disable all clkreq of PCIe root ports as SMARC interface do not
    # have this pins.