[coreboot-gerrit] Change in coreboot[master]: drv/intel/gma/opregion: Add interface for GNVS ASLB handling

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20435

Change subject: drv/intel/gma/opregion: Add interface for GNVS ASLB handling
......................................................................

drv/intel/gma/opregion: Add interface for GNVS ASLB handling

Add new interface to set and get GNVS' ASLB register.
To be used by Intel's gma driver to set ASLB at ACPI table
creation and to get ASLB on S3 resume.

Change-Id: If30c6b2270069783b0892774802f47406404da5f
Signed-off-by: Patrick Rudolph 
---
M src/drivers/intel/gma/opregion.h
M src/northbridge/intel/fsp_sandybridge/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/sandybridge/gma.c
5 files changed, 54 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/20435/1

diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h
index c590805..ff64aec 100644
--- a/src/drivers/intel/gma/opregion.h
+++ b/src/drivers/intel/gma/opregion.h
@@ -246,5 +246,7 @@
 } __attribute__((packed)) optionrom_vbt_t;

void intel_gma_opregion_register(uintptr_t opregion);
+uintptr_t gma_get_gnvs_aslb(const void *gnvs);
+void gma_set_gnvs_aslb(const void *gnvs, uintptr_t aslb);

#endif /* _COMMON_GMA_H_ */
diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c
index 8e2d968..daff050 100644
--- a/src/northbridge/intel/fsp_sandybridge/gma.c
+++ b/src/northbridge/intel/fsp_sandybridge/gma.c
@@ -53,6 +53,19 @@
    return new_vendev;
 }

+uintptr_t gma_get_gnvs_aslb(const void *gnvs)
+{
+	const global_nvs_t gnvs_ptr = gnvs;
+	return gnvs_ptr ? (uintptr_t)gnvs_ptr->aslb : NULL;
+}
+
+void gma_set_gnvs_aslb(const void *gnvs, uintptr_t aslb)
+{
+	const global_nvs_t gnvs_ptr = gnvs;
+	if (gnvs_ptr)
+		gnvs_ptr->aslb = (u32)aslb;
+}
+
 static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
    if (!vendor || !device) {
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index f22ff48..709c46b 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -215,6 +215,19 @@
    return 0;
 }

+uintptr_t gma_get_gnvs_aslb(const void *gnvs)
+{
+	const global_nvs_t gnvs_ptr = gnvs;
+	return gnvs_ptr ? (uintptr_t)gnvs_ptr->aslb : NULL;
+}
+
+void gma_set_gnvs_aslb(const void *gnvs, uintptr_t aslb)
+{
+	const global_nvs_t gnvs_ptr = gnvs;
+	if (gnvs_ptr)
+		gnvs_ptr->aslb = (u32)aslb;
+}
+
 static void power_well_enable(void)
 {
    gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE);
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index fa84f78..2aeec70 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -304,6 +304,19 @@
    return 0;
 }

+uintptr_t gma_get_gnvs_aslb(const void *gnvs)
+{
+	const global_nvs_t gnvs_ptr = gnvs;
+	return gnvs_ptr ? (uintptr_t)gnvs_ptr->aslb : NULL;
+}
+
+void gma_set_gnvs_aslb(const void *gnvs, uintptr_t aslb)
+{
+	const global_nvs_t gnvs_ptr = gnvs;
+	if (gnvs_ptr)
+		gnvs_ptr->aslb = (u32)aslb;
+}
+
 static void gma_pm_init_pre_vbios(struct device *dev)
 {
    u32 reg32;
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 9611e64..0f91be0 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -311,6 +311,19 @@
    return 0;
 }

+uintptr_t gma_get_gnvs_aslb(const void *gnvs)
+{
+	const global_nvs_t gnvs_ptr = gnvs;
+	return gnvs_ptr ? (uintptr_t)gnvs_ptr->aslb : NULL;
+}
+
+void gma_set_gnvs_aslb(const void *gnvs, uintptr_t aslb)
+{
+	const global_nvs_t gnvs_ptr = gnvs;
+	if (gnvs_ptr)
+		gnvs_ptr->aslb = (u32)aslb;
+}
+
 static void gma_pm_init_pre_vbios(struct device *dev)
 {
    u32 reg32;