Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )
Change subject: soc/intel/tigerlake: Update chip files ......................................................................
Patch Set 6:
(5 comments)
I am working on other review comments to get fixed.
https://review.coreboot.org/c/coreboot/+/37783/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37783/6//COMMIT_MSG@11 PS6, Line 11: update soc_intel_tigerlake_config struct
What is the motivation behind this update? I see some of the configs being dropped from this struct, […]
Yes, we are planning on adding configs per feature enabling instead of bulk landing.
About unused configs, we will clean up in this patch as necessary.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 257: gpio_override_pm
Why are these removed? These are required on TGL as well.
Ack
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 39: GPP_[A:G]
Is this correct?
Ack
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 180: ProbeTypeDisable = 0x00,
Why is 0x01 missing?
This is in sync with FSP settings where is 0x01 is not used.
https://review.coreboot.org/c/coreboot/+/37783/6/src/soc/intel/tigerlake/chi... PS6, Line 187: ProbeTypeMax
Do you want ProbeTypeMax to be ProbeTypeManual?
Ack