[coreboot-gerrit] [L] Change in coreboot[main]: soc/intel/skylake: Drop redundant PcieRpEnable

[Angel Pons (Code Review)]

Attention is currently required from: Jan Samek, Jeremy Soller, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Reagan, Sean Rhodes, Tim Crawford.

Angel Pons has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email )

Change subject: soc/intel/skylake: Drop redundant PcieRpEnable
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Patch Set 2:

(1 comment)

File src/mainboard/razer/blade_stealth_kbl/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/79917/comment/87cea7d1_455f2410?usp... :
PS2, Line 190: 		device ref pcie_rp1	on  end
> > The PCI specification says that multi-function devices must always implement function 0. […]

Ah, if `PcieRpEnable` is not set for RP1, then `pcie_rp1` can indeed be dropped then.