[coreboot-gerrit] New patch to review for coreboot: soc/intel/skylake: Add GSPI controller get configuration callback

[Furquan Shaikh]

Furquan Shaikh ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18338

-gerrit

commit c3796cd975f115e34e5088d9d9aa7801f7d3b0fe
Author: Furquan Shaikh 
Date:   Sun Jan 8 13:39:08 2017 -0800

soc/intel/skylake: Add GSPI controller get configuration callback

BUG=chrome-os-partner:59832

Change-Id: I5170076c15d72a7f29acd0989acef5b9149e2ba0
    Signed-off-by: Furquan Shaikh 
---
 src/soc/intel/skylake/spi.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c
index a8a83c6..ddff4dc 100644
--- a/src/soc/intel/skylake/spi.c
+++ b/src/soc/intel/skylake/spi.c
@@ -33,8 +33,31 @@ static const struct spi_ctrlr flash_spi_ctrlr = {
    .setup = flash_spi_ctrlr_setup,
 };

+static int gspi_ctrlr_get_config(const struct spi_slave *dev,
+				struct spi_cfg *cfg)
+{
+	if (dev->cs != 0) {
+		printk(BIOS_ERR, "%s: Unsupported device "
+		       "bus=0x%x,cs=0x%x!\n", __func__, dev->bus, dev->cs);
+		return -1;
+	}
+
+	cfg->clk_phase = SPI_CLOCK_PHASE_FIRST;
+	cfg->clk_polarity = SPI_POLARITY_LOW;
+	cfg->cs_polarity = SPI_POLARITY_LOW;
+	cfg->wire_mode = SPI_4_WIRE_MODE;
+	cfg->data_bit_length = 8;
+
+	return 0;
+}
+
+static const struct spi_ctrlr gspi_ctrlr = {
+	.get_config = gspi_ctrlr_get_config,
+};
+
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
    { .ctrlr = &flash_spi_ctrlr, .bus_start = 0, .bus_end = 0 },
+	{ .ctrlr = &gspi_ctrlr, .bus_start = 1, .bus_end = 2 },
 };

const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);