Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34662 )
Change subject: Documentation/binaries: Add AMD FSP documentation ......................................................................
Patch Set 2:
(8 comments)
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... File Documentation/binaries/AMD_FSP_family_17h.md:
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 22: inittialized
spelling
Ack
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 27: . **FSP-M can be made position independent** : Because it's loaded to memory and does not uses CAR, FSP-M can be made PIC : (Position Independent Code).
I would find a way to reword the statement, then, because the Intel FSP can also be loaded to memory […]
Will try.
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 37: 3. **UPD with no UEFI dependencies** : UPD interface can be made C99 or C11 compatible with no hard dependencies : to UEFI.
Is this from a recent conversation or from some of the early planning documents? Things have been e […]
From a spread sheet he filled up yesterday... you can see what he wrote.
https://review.coreboot.org/c/coreboot/+/34662/1/Documentation/binaries/AMD_... PS1, Line 40: 4. **Platform specific code**
It's not designed into the interface definition, but the Ice Lake implementation can pass in a point […]
Needs more discussion
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/amd/... File Documentation/binaries/amd/AMD_FSP_family_17h.md:
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/amd/... PS2, Line 12: * Reset vector is not the old 0xFFFFFFF0.
Expand on this some?
Marshall suggested pointing to family 17h (link), will that suffice?
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/amd/... PS2, Line 25: PSP can be made to load a section of the flash into RAM
Maybe "The PSP typically loads the boot vector and associated code into RAM"? […]
Will do.
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/amd/... PS2, Line 40: 4. **Platform specific code** : Similar to AGESA, FSP will make call back to platform specific code. :
Hrm. This is the first I've heard of this, and could create significant problems. […]
I don't know, ask Alex at conference call today. The document he provided me was vague...
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/cavi... File Documentation/binaries/cavium/index.md:
https://review.coreboot.org/c/coreboot/+/34662/2/Documentation/binaries/cavi... PS2, Line 7: ## Platform initialization : - [AMD FSP](AMD_FSP_family_17h.md)
What does this have to do with cavium?
Should have been removed when I copy/pasted... will remove.