9 Jan
2021
9 Jan
'21
5:16 a.m.
Attention is currently required from: Felix Singer, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49136 )
Change subject: soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs ......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49136/comment/ef70c9d3_664b5002 PS7, Line 16: RP1: PEG60 : 0:6:0 : CPU SSD1 : RP2: PEG10 : 0:1:0 : x8 CPU Slot : RP3: PEG62 : 0:6:2 : CPU SSD2 This seems to match ADL-P only. Is ADL-S generally not supported?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Gerrit-Change-Number: 49136
Gerrit-PatchSet: 7
Gerrit-Owner: Subrata Banik subrata.banik@intel.com
Gerrit-Reviewer: Felix Singer felixsinger@posteo.net
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