HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32943
Change subject: sb/intel/bd82x6x/early_pch.c: Remove variable set but not used ......................................................................
sb/intel/bd82x6x/early_pch.c: Remove variable set but not used
Change-Id: If359eaa010949427dbff1e3a83528c0ad399dc9d Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 15 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32943/1
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e74c304..883a4aa 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -40,7 +40,6 @@ static u32 read_iobp(u32 address) { - volatile u32 tmp; u32 ret;
RCBA32(IOBPIRI) = address; @@ -48,14 +47,13 @@ wait_iobp(); ret = RCBA32(IOBPD); wait_iobp(); - tmp = RCBA8(IOBPS); // call wait_iobp() instead here? + RCBA8(IOBPS); // call wait_iobp() instead here? return ret; }
static void write_iobp(u32 address, u32 val) { - volatile u32 tmp; /* this function was probably pch_iobp_update with the andvalue * being 0. So either the IOBP read can be removed or this function * and the pch_iobp_update function in ramstage could be merged */ @@ -67,7 +65,7 @@ wait_iobp(); RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600;
- tmp = RCBA8(IOBPS); // call wait_iobp() instead here? + RCBA8(IOBPS); // call wait_iobp() instead here? }
void early_pch_init_native_dmi_pre(void) @@ -84,14 +82,12 @@
void early_pch_init_native_dmi_post(void) { - volatile u32 tmp; - - tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050); // !!! = 0x01200654 RCBA32(0x0050) = 0x01200654; - tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050); // !!! = 0x01200654 RCBA32(0x0050) = 0x012a0654; - tmp = RCBA32(0x0050); // !!! = 0x012a0654 - tmp = RCBA8(0x1114); // !!! = 0x00 + RCBA32(0x0050); // !!! = 0x012a0654 + RCBA8(0x1114); // !!! = 0x00 RCBA8(0x1114) = 0x05;
/* @@ -118,7 +114,7 @@ */ RCBA32(0x2020) = (1 << 31) | (1 << 24) | (0x11 << 1); /* Read back register */ - tmp = RCBA32(0x2020); + RCBA32(0x2020);
/* Virtual Channel private Resource Control Register. * Enable channel. @@ -127,7 +123,7 @@ */ RCBA32(0x2030) = (1 << 31) | (2 << 24) | (0x22 << 1); /* Read back register */ - tmp = RCBA32(0x2030); + RCBA32(0x2030);
/* Virtual Channel ME Resource Control Register. * Enable channel. @@ -139,7 +135,7 @@ /* Lock Virtual Channel Resource control register. */ RCBA32(0x0050) |= 0x80000000; /* Read back register */ - tmp = RCBA32(0x0050); + RCBA32(0x0050);
/* Wait for virtual channels negotiation pending */ while (RCBA16(0x201a) & VCNEGPND) @@ -155,24 +151,23 @@ void early_pch_init_native (void) { - volatile u32 tmp; pci_write_config8 (SOUTHBRIDGE, 0xa6, pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2);
RCBA32(0x2088) = 0x00109000; - tmp = RCBA32(0x20ac); // !!! = 0x00000000 + RCBA32(0x20ac); // !!! = 0x00000000 RCBA32(0x20ac) = 0x40000000; RCBA32(0x100c) = 0x01110000; RCBA8(0x2340) = 0x1b; - tmp = RCBA32(0x2314); // !!! = 0x0a080000 + RCBA32(0x2314); // !!! = 0x0a080000 RCBA32(0x2314) = 0x0a280000; - tmp = RCBA32(0x2310); // !!! = 0xc809605b + RCBA32(0x2310); // !!! = 0xc809605b RCBA32(0x2310) = 0xa809605b; RCBA32(0x2324) = 0x00854c74; - tmp = RCBA8(0x0400); // !!! = 0x00 - tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA8(0x0400); // !!! = 0x00 + RCBA32(0x2310); // !!! = 0xa809605b RCBA32(0x2310) = 0xa809605b; - tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA32(0x2310); // !!! = 0xa809605b RCBA32(0x2310) = 0xa809605b;
write_iobp(0xea007f62, 0x00590133);