[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Add ISST override support

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41429 )

Change subject: soc/intel/jasperlake: Add ISST override support
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soc/intel/jasperlake: Add ISST override support

Add support for mainboard to override Intel Speed Shift Technology
(ISST). This will allow the mainboards to override default ISST
configuration during the phases where it is not supported.

BUG=b:151281860
TEST=Build and boot the mainboard.

Change-Id: I811cb2a3d4ee3a7e8689601a1d440547633f5885
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/jasperlake/cpu.c
M src/soc/intel/jasperlake/include/soc/cpu.h
2 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/41429/1

diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 2533fe0..30023e9 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -29,6 +29,7 @@
    config_t *conf = config_of_soc();
    msr_t msr;

+	mainboard_isst_override();
    if (conf->speed_shift_enable) {
    	/*
    	 * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
@@ -247,3 +248,8 @@
    if (mp_init_with_smm(cpu_bus, &mp_ops))
    	printk(BIOS_ERR, "MP initialization failure.\n");
 }
+
+__weak void mainboard_isst_override(void)
+{
+	/* Nothing to override. */
+}
diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h
index 58e9a8f..b4faaac 100644
--- a/src/soc/intel/jasperlake/include/soc/cpu.h
+++ b/src/soc/intel/jasperlake/include/soc/cpu.h
@@ -33,4 +33,7 @@
 /* Configure power limits for turbo mode */
 void set_power_limits(u8 power_limit_1_time);

+/* Mainboard Intel Speed Shift Technology override */
+void mainboard_isst_override(void);
+
 #endif