Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45578 )
Change subject: mb/hp: Add HP EliteBook Folio 9480m ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45578/8/src/mainboard/hp/folio_9480... File src/mainboard/hp/folio_9480m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45578/8/src/mainboard/hp/folio_9480... PS8, Line 39: sata_port0_gen3_dtle
I can get from dmesg that SATA and M.2 ports are ata2 and ata4, and the current sata_port_map works. […]
Oh, nice. According to Broadwell code, the port0 and port1 DTLE settings are backwards.
Lynxpoint: #define SATA_IOBP_SP0DTLE_DATA 0xea002550 #define SATA_IOBP_SP0DTLE_EDGE 0xea002554 #define SATA_IOBP_SP1DTLE_DATA 0xea002750 #define SATA_IOBP_SP1DTLE_EDGE 0xea002754
Broadwell: #define SATA_IOBP_SP0DTLE_DATA 0xea002750 #define SATA_IOBP_SP0DTLE_EDGE 0xea002754 #define SATA_IOBP_SP1DTLE_DATA 0xea002550 #define SATA_IOBP_SP1DTLE_EDGE 0xea002554 #define SATA_IOBP_SP2DTLE_DATA 0xea002350 #define SATA_IOBP_SP2DTLE_EDGE 0xea002354 #define SATA_IOBP_SP3DTLE_DATA 0xea002150 #define SATA_IOBP_SP3DTLE_EDGE 0xea002154