Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5385
-gerrit
commit b4fb09ddfea4d7c805af4842b374b99fdb65142e Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Fri Mar 14 01:06:22 2014 +1100
drivers/hwm: Add a generic hwm driver.
Make generic, testing with Fintek Super I/O.... currently wired in to fintek superio, need to move ararry of values to mainboard.c and fix linkage issue???
Change-Id: Ic7bdea55907e379aad9e74b87b514e8038ef9fd0 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/hwm/Kconfig | 6 ++ src/drivers/hwm/Makefile.inc | 20 ++++ src/drivers/hwm/superio_hwm.c | 117 +++++++++++++++++++++++ src/include/hwm/superio_hwm.h | 32 +++++++ src/mainboard/jetway/nf81-t56n-lf/Kconfig | 5 + src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 5 + src/superio/fintek/f71869ad/chip.h | 1 + src/superio/fintek/f71869ad/superio.c | 32 ++++++- 10 files changed, 218 insertions(+), 2 deletions(-)
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 5267ff8..c09e57f 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -22,6 +22,7 @@ source src/drivers/dec/Kconfig source src/drivers/elog/Kconfig source src/drivers/emulation/Kconfig source src/drivers/generic/Kconfig +source src/drivers/hwm/Kconfig source src/drivers/i2c/Kconfig source src/drivers/ics/Kconfig source src/drivers/intel/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 197a900..4b944cb 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -39,3 +39,4 @@ subdirs-y += ipmi subdirs-y += elog subdirs-y += xpowers subdirs-$(CONFIG_ARCH_X86) += pc80 +subdirs-$(CONFIG_ARCH_X86) += hwm diff --git a/src/drivers/hwm/Kconfig b/src/drivers/hwm/Kconfig new file mode 100644 index 0000000..dc60fd7 --- /dev/null +++ b/src/drivers/hwm/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_SUPERIO_HWM + bool "Super I/O HWM" + default n + help + Just enough of a driver to make coreboot control system fans. + No configuration is necessary for the OS to pick up the device. diff --git a/src/drivers/hwm/Makefile.inc b/src/drivers/hwm/Makefile.inc new file mode 100644 index 0000000..ccb6de0 --- /dev/null +++ b/src/drivers/hwm/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_DRIVERS_SUPERIO_HWM) += superio_hwm.c diff --git a/src/drivers/hwm/superio_hwm.c b/src/drivers/hwm/superio_hwm.c new file mode 100644 index 0000000..407a36f --- /dev/null +++ b/src/drivers/hwm/superio_hwm.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all Fintek Super I/O HWM's. */ +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include <stdlib.h> +#include <hwm/superio_hwm.h> + +/* Helper functions */ +static void pnp_write_index(u16 port, u8 reg, u8 value) +{ + outb(reg, port); + outb(value, port + 1); +} + +static u8 pnp_read_index(u16 port, u8 reg) +{ + outb(reg, port); + return inb(port + 1); +} +/* .. */ + +/* Initialize F71869AD hardware monitor registers, which are at 0x225. */ +/* XXX: make configurable.. */ +static void init_registers(u16 base) +{ + u8 reg, value; + int i; + + /* XXX: work out correct values??? */ + u8 hwm_reg_values[] = { + /* reg mask data */ + 0xaf, 0x93, 0x8c, /* FAN1_TEMP_SEL p.73 */ + 0xef, 0x00, 0x02, /* SMB_Protocal p.83 */ + }; + + for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { + reg = hwm_reg_values[i]; + value = pnp_read_index(base, reg); + value &= 0xff & hwm_reg_values[i + 1]; + value |= 0xff & hwm_reg_values[i + 2]; + printk(BIOS_DEBUG, "Super I/O HWM: base = 0x%04x, reg = 0x%02x, " + "value = 0x%02x\n", base, reg, value); + pnp_write_index(base, reg, value); + } +} +/* .. */ + +/* Main driver */ +void hwm_init(device_t dev) +{ + if (!CONFIG_DRIVERS_SUPERIO_HWM) + return; + + /* return if hwm is disabled in devicetree.cb */ + struct drivers_superio_hwm_config *config = dev->chip_info; + if (!dev->enabled || !config) + return; + + u32 hwm_base = config->base; + + printk(BIOS_DEBUG, "Super I/O HWM: Initializing Hardware Monitor at pci %04x\n" + , hwm_base); + + struct resource *res = find_resource(dev, PNP_IDX_IO0); + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + printk(BIOS_DEBUG, "Super I/O HWM: Base Address at 0x%x\n", (u32)res->base); + printk(BIOS_WARNING, "Super I/O HWM: Configuring registers...\n"); + init_registers(res->base); +} + +/* +static void hwm_noop(device_t dummy) +{ +} + +static struct device_operations hwm_ops = { + .read_resources = hwm_noop, + .set_resources = hwm_noop, + .enable_resources = hwm_noop, + .init = hwm_init, +}; + +static void enable_dev(device_t dev) +{ + dev->ops = &hwm_ops; +} + +struct chip_operations hwm_fintek_ops = { + CHIP_NAME("Super I/O Hardware Monitor.") + .enable_dev = enable_dev +}; +*/ diff --git a/src/include/hwm/superio_hwm.h b/src/include/hwm/superio_hwm.h new file mode 100644 index 0000000..49e431c --- /dev/null +++ b/src/include/hwm/superio_hwm.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan eocallaghan@alterapraxis.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DRIVERS_SUPERIO_HWM_H +#define DRIVERS_SUPERIO_HWM_H + +#include <device/device.h> + +/* Initialization parameters?? */ +typedef struct drivers_superio_hwm_config { + u32 base; +} hwm_config_t; + +void hwm_init(device_t dev); + +#endif /* DRIVERS_SUPERIO_HWM_H */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index 6fbd75c..1429d9e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_FINTEK_F71869AD + select SB_SUPERIO_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE @@ -113,4 +114,8 @@ config DRIVERS_PS2_KEYBOARD bool default y
+config DRIVERS_SUPERIO_HWM + bool + default y + endif # BOARD_JETWAY_NF81_T56N_LF diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index ce08bee..35769df 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -257,4 +257,9 @@ static const CODECTBLLIST codec_tablelist[] = */ #define FADT_PM_PROFILE 1
+/** + * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + */ +#define SIO_HWM_BASE_ADDRESS 0x225 + #endif /* _PLATFORM_CFG_H_ */ diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 5b18c33..fe5be17 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -21,6 +21,7 @@ #ifndef SUPERIO_FINTEK_F71869AD_CHIP_H #define SUPERIO_FINTEK_F71869AD_CHIP_H
+#include <hwm/superio_hwm.h> #include <pc80/keyboard.h> #include <device/device.h>
diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 11ad6f8..6b8c71e 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -37,16 +37,44 @@ static void f71869ad_init(device_t dev)
switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ + case F71869AD_HWM: + hwm_init(dev); + break; case F71869AD_KBC: pc_keyboard_init(&conf->keyboard); break; } }
+static void enable_hwm_smbus(device_t dev) +{ + u8 reg8; + + /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI). */ + reg8 = pnp_read_config(dev, 0x0a); + reg8 ^= 0x42; /* p.54 mask bits 1 and 6 Intel -> AMD mode */ + pnp_write_config(dev, 0x0a, reg8); +} + +static void f71869ad_pnp_enable_resources(device_t dev) +{ + pnp_enable_resources(dev); + + pnp_enter_conf_mode(dev); + switch(dev->path.pnp.device) { + case F71869AD_HWM: + printk(BIOS_DEBUG, "F71869AD HWM SMBus enabled\n"); + enable_hwm_smbus(dev); + break; + } + pnp_exit_conf_mode(dev); +} + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, +// .enable_resources = pnp_enable_resources, + .enable_resources = f71869ad_pnp_enable_resources, .enable = pnp_alt_enable, .init = f71869ad_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa, @@ -109,7 +137,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71869AD_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, { &ops, F71869AD_GPIO, }, { &ops, F71869AD_BSEL, PNP_IO0, {0x07f8, 0}, },