[coreboot-gerrit] [S] Change in coreboot[main]: arch/x86/cpu: Add helper function to compute cache

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85638?usp=email )

Change subject: arch/x86/cpu: Add helper function to compute cache
......................................................................

arch/x86/cpu: Add helper function to compute cache

Consider special requirements for computing cache size in certain SoCs,
such as `soc/amd/glinda`.

Use the helper function to implement SoC-specific logic for computing
cache size.

Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449
Signed-off-by: Naresh Solanki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85638
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
Reviewed-by: Angel Pons 
---
M src/arch/x86/Kconfig
M src/arch/x86/cpu_common.c
M src/arch/x86/include/arch/cpu.h
3 files changed, 29 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 7ef1a6d..d78aa8f 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -453,4 +453,10 @@
    help
      For platforms without writable PAM-F segment support. Put ROM table
      pointers (e.g. ACPI/SMBIOS low pointers) into EBDA.
+
+config SOC_FILL_CPU_CACHE_INFO
+	bool
+	default n
+	help
+	  SoC selects this if it implements soc_fill_cpu_cache_info.
 endif
diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c
index 5f7cd5d..d7d701d 100644
--- a/src/arch/x86/cpu_common.c
+++ b/src/arch/x86/cpu_common.c
@@ -212,11 +212,8 @@
    return (cpuid_edx(5) >> (state * 4)) & 0xf;
 }

-bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info)
+bool x86_get_cpu_cache_info(uint8_t level, struct cpu_cache_info *info)
 {
-	if (!info)
-		return false;
-
    uint32_t leaf = cpu_get_cache_info_leaf();
    if (!leaf)
    	return false;
@@ -235,6 +232,16 @@

return true;
 }
+bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info)
+{
+	if (!info)
+		return false;
+
+	if (CONFIG(SOC_FILL_CPU_CACHE_INFO))
+		return soc_fill_cpu_cache_info(level, info);
+
+	return x86_get_cpu_cache_info(level, info);
+}

bool is_cache_sets_power_of_two(void)
 {
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 8bc6a18..3685561 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -331,6 +331,18 @@
 bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info);

/*
+ * soc_fill_cpu_cache_info is SoC specific implementation for fill_cpu_cache_info.
+ * This is intended to compute cache size for a particular level when generic
+ * implementation isn't accurate.
+ * Returns True if SoC handler was success else return False.
+ */
+bool soc_fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info);
+
+/*
+ * x86_get_cpu_cache_info is generic x86 implementation.
+ */
+bool x86_get_cpu_cache_info(uint8_t level, struct cpu_cache_info *info);
+/*
  * Determines whether the number of cache sets is a power of two.
  *
  * Cache designs often favor power-of-two set counts for efficient indexing