[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Make changes to support S3

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Duncan Laurie.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48682 )

Change subject: soc/intel/common/block/pcie/rtd3: Make changes to support S3
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Patch Set 2:

(1 comment)

File src/soc/intel/common/block/pcie/rtd3/rtd3.c:

https://review.coreboot.org/c/coreboot/+/48682/comment/6cc211e1_8da3e8ab 
PS2, Line 91: /* Ensure check works for both active low and active high GPIOs. */
            : 	acpigen_write_store_int_to_op(gpio->active_low, LOCAL1_OP);
            : 
            : 	acpigen_write_if_lequal_op_op(LOCAL0_OP, LOCAL1_OP);
            : 	acpigen_write_store_int_to_op(0, LOCAL0_OP);
            : 	acpigen_pop_len(); /* If */
            : 	acpigen_write_else();
            : 	acpigen_write_store_int_to_op(1, LOCAL0_OP);
            : 	acpigen_pop_len(); /* Else */
doesn't acpigen_get_tx_gpio already take care of the polarity inversion?