[coreboot-gerrit] Change in coreboot[master]: northbridge/amd/lx: Fix function setShadowRCONF

[Iru Cai (Code Review)]

Iru Cai has uploaded this change for review. ( https://review.coreboot.org/20808

Change subject: northbridge/amd/lx: Fix function setShadowRCONF
......................................................................

northbridge/amd/lx: Fix function setShadowRCONF

GCC found an int-in-bool-context in northbridgeinit.c. The logical
`&&` in `if (shadowByte && (1 << bit))` should be changed to bitwise
`&`.

Change-Id: I7d7720121d4730254542372282f5561739e7214b
Signed-off-by: Iru Cai 
---
M src/northbridge/amd/lx/northbridgeinit.c
1 file changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/20808/1

diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index f588ead..5d97c08 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -488,7 +488,7 @@
    for (bit = 8; (bit > 4); bit--) {
    	msr.hi <<= 8;
    	msr.hi |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte && (1 << bit))
+		if (shadowByte & (1 << bit))
    		msr.hi |= 0x20;	// write serialize PCI memory
    }

@@ -496,7 +496,7 @@
    for (; bit; bit--) {
    	msr.lo <<= 8;
    	msr.lo |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte && (1 << bit))
+		if (shadowByte & (1 << bit))
    		msr.lo |= 0x20;	// write serialize PCI memory
    }

@@ -508,7 +508,7 @@
    for (bit = 8; (bit > 4); bit--) {
    	msr.hi <<= 8;
    	msr.hi |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte && (1 << bit))
+		if (shadowByte & (1 << bit))
    		msr.hi |= 0x20;	// write serialize PCI memory
    }

@@ -516,7 +516,7 @@
    for (; bit; bit--) {
    	msr.lo <<= 8;
    	msr.lo |= 1;	// cache disable PCI/Shadow memory
-		if (shadowByte && (1 << bit))
+		if (shadowByte & (1 << bit))
    		msr.lo |= 0x20;	// write serialize PCI memory
    }