Attention is currently required from: Philipp Hug.
Hello Philipp Hug,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81306?usp=email
to look at the new patch set (#3).
Change subject: WIP: simple, dumb, illegal instruction handling ......................................................................
WIP: simple, dumb, illegal instruction handling
This is a very simple example of an illegal instruction handler.
coreboot SBI is designed to minimize SBI functionality. This minimization is reflected in the lack of generality in the code. The ill() function switches out on a subset of instrution types, because C compilers tend to use a very limited subset of the possibilities of an instruction.
In this case, code will support only two illegal instructions: csrrs x10, time, x0 csrrs x14, time, x0
On modern RISC-V systems, the trap will not even occur. At some point RISC-V community figured out that trapping on reading time was not always the best idea :-)
So, in general, on future systems, reads will not trap.
This CL can not go in until Hug's menvcfg support goes in.
Signed-off-by: Ronald G Minnich rminnich@gmail.com
Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 --- M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c 2 files changed, 50 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81306/3