[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Enable CPU PCIe RP 2

[Meera Ravindranath (Code Review)]

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59392 )

Change subject: mb/intel/adlrvp: Enable CPU PCIe RP 2
......................................................................

mb/intel/adlrvp: Enable CPU PCIe RP 2

Disabling CPU PCIe RP 2 causes regression in NVMe boot
on ADL-P RVP boards.

Signed-off-by: Meera Ravindranath 
Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882
---
M src/mainboard/intel/adlrvp/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/59392/1

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 8926887..1205234 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -48,6 +48,12 @@
    	.flags = PCIE_RP_CLK_REQ_DETECT,
    }"

+	# Enable CPU PCIE RP 2 using CLK 3
+	register "cpu_pcie_rp[CPU_RP(2)]" = "{
+		.clk_req = 3,
+		.clk_src = 3,
+	}"
+
    # Enable PCH PCIE RP 6 using CLK 5
    register "pch_pcie_rp[PCH_RP(6)]" = "{
    	.clk_src = 5,