Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43744 )
Change subject: haswell: Set up Root Complex topology ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43744/2/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/northbridge.c:
https://review.coreboot.org/c/coreboot/+/43744/2/src/northbridge/intel/haswe... PS2, Line 471: dev = pcidev_on_root(1, 0); : if (dev && dev->enabled) { : : EPBAR32(EPLE2A) = 0x8000; : EPBAR32(EPLE2D) = (1 << 16) | 1; : : pci_write_config32(dev, PEG_ESD, (1 << 16)); : pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); : pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); : : /* Read and write to lock register */ : pci_or_config32(dev, PEG_DCAP2, 0); : } : : dev = pcidev_on_root(1, 1); : if (dev && dev->enabled) { : : EPBAR32(EPLE3A) = 0x9000; : EPBAR32(EPLE3D) = (1 << 16) | 1; : : pci_write_config32(dev, PEG_ESD, (1 << 16)); : pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); : pci_write_config32(dev, PEG_LE1D, (1 << 16) | 1); : : /* Read and write to lock register */ : pci_or_config32(dev, PEG_DCAP2, 0); : } : : dev = pcidev_on_root(1, 2)
I can't use the EPLExA/EPLExD macros then. […]
Done