Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46402 )
Change subject: soc/mediatek/mt8192: devapc: add basic devapc drivers ......................................................................
soc/mediatek/mt8192: devapc: add basic devapc drivers
Add basic devapc (device access permission control) drivers.
DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver.
Change-Id: I2ad47c86b88047c76854a6f8a67b251b6a9d4013 Signed-off-by: Nina Wu nina-cm.wu@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46402 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/devapc.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/devapc.h M src/soc/mediatek/mt8192/soc.c 5 files changed, 117 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index a81e532..415acf3 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -40,6 +40,7 @@
ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c +ramstage-y += devapc.c ramstage-y += dpm.c ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += flash_controller.c diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c new file mode 100644 index 0000000..77d5fc5 --- /dev/null +++ b/src/soc/mediatek/mt8192/devapc.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/devapc.h> + +static void *getreg(uintptr_t base, unsigned int offset) +{ + return (void *)(base + offset); +} + +static void infra_master_init(uintptr_t base) +{ + /* Sidband */ + SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, 1, CPU_EB_SEC, 1); + + /* Domain */ + SET32_BITFIELDS(getreg(base, MAS_SEC_0), PCIE_DOM, MAS_DOMAIN_1); + SET32_BITFIELDS(getreg(base, MAS_DOM_1), SCP_SSPM_DOM, MAS_DOMAIN_2, + CPU_EB_DOM, MAS_DOMAIN_2); +} + +static void peri_master_init(uintptr_t base) +{ + /* Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_0), SPM_DOM, MAS_DOMAIN_2); +} + +static uintptr_t devapc_base[DEVAPC_AO_MAX] = { + DEVAPC_INFRA_AO_BASE, + DEVAPC_PERI_AO_BASE, + DEVAPC_PERI2_AO_BASE, + DEVAPC_PERI_PAR_AO_BASE, + DEVAPC_FMEM_AO_BASE, +}; + +static void (*master_init[DEVAPC_AO_MAX])(uintptr_t) = { + infra_master_init, + peri_master_init, +}; + +void dapc_init(void) +{ + int i; + uintptr_t devapc_ao_base; + + for (i = 0; i < ARRAY_SIZE(devapc_base); i++) { + devapc_ao_base = devapc_base[i]; + + /* Init dapc */ + write32(getreg(devapc_ao_base, AO_APC_CON), 0x0); + write32(getreg(devapc_ao_base, AO_APC_CON), 0x1); + + /* Init master */ + if (master_init[i]) + master_init[i](devapc_ao_base); + } +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 7660bcc..e4d57b0 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -28,6 +28,11 @@ PMIF_SPMI_BASE = IO_PHYS + 0x00027000, PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, + DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, + DEVAPC_PERI_AO_BASE = IO_PHYS + 0x00034000, + DEVAPC_PERI2_AO_BASE = IO_PHYS + 0x00038000, + DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0003C000, + DEVAPC_FMEM_AO_BASE = IO_PHYS + 0x00044000, I2C_DMA_BASE = IO_PHYS + 0x00217080, EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, diff --git a/src/soc/mediatek/mt8192/include/soc/devapc.h b/src/soc/mediatek/mt8192/include/soc/devapc.h new file mode 100644 index 0000000..f227aaa --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/devapc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_DEVAPC_H +#define SOC_MEDIATEK_MT8192_DEVAPC_H + +#include <device/mmio.h> +#include <soc/addressmap.h> + +void dapc_init(void); + +#define DEVAPC_AO_MAX 6 + +enum devapc_ao_offset { + MAS_DOM_0 = 0x0900, + MAS_DOM_1 = 0x0904, + MAS_SEC_0 = 0x0A00, + AO_APC_CON = 0x0F00, +}; + +/* INFRA */ +DEFINE_BIT(SCP_SSPM_SEC, 3) +DEFINE_BIT(CPU_EB_SEC, 4) + +DEFINE_BITFIELD(PCIE_DOM, 19, 16) /* 2 */ +DEFINE_BITFIELD(SCP_SSPM_DOM, 3, 0) /* 4 */ +DEFINE_BITFIELD(CPU_EB_DOM, 11, 8) /* 5 */ + +/* PERI */ +DEFINE_BITFIELD(SPM_DOM, 3, 0) /* 0 */ + +enum master_domain { + MAS_DOMAIN_0 = 0, + MAS_DOMAIN_1, + MAS_DOMAIN_2, + MAS_DOMAIN_3, + MAS_DOMAIN_4, + MAS_DOMAIN_5, + MAS_DOMAIN_6, + MAS_DOMAIN_7, + MAS_DOMAIN_8, + MAS_DOMAIN_9, + MAS_DOMAIN_10, + MAS_DOMAIN_11, + MAS_DOMAIN_12, + MAS_DOMAIN_13, + MAS_DOMAIN_14, + MAS_DOMAIN_15, + MAS_DOMAIN_MAX, +}; + + +#endif /* SOC_MEDIATEK_MT8192_DEVAPC_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 8696f34..883f4dc 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h> +#include <soc/devapc.h> #include <soc/emi.h> #include <soc/mcupm.h> #include <soc/mmu_operations.h> @@ -16,6 +17,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + dapc_init(); mcupm_init(); sspm_init(); ufs_disable_refclk();