[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP

[Cliff Huang (Code Review)]

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55150 )

Change subject: soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP
......................................................................

soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP

This is to enable S0ix device specific method _DSM ( UUID:
57a6512e-3979-4e9d-9708-ff13b2508972) for Intel Power Engine Plug-in.

Alone with this change, one coreboot and two kernel changes are also
required:
https://review.coreboot.org/c/coreboot/+/55127
https://chromium-review.googlesource.com/2800280
https://chromium-review.googlesource.com/2800281

Once done, substate_requirement_registers is created under
/sys/kernel/debug/pmc_core/
Use: 'cat /sys/kernel/debug/pmc_core/substate_requirement_registers' to
check the content.

Signed-off-by: Cliff Huang 
Change-Id: I127c695eed9e2842996381c7559695f289cf4585
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/55150/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 79e775d..eb62b11 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -80,6 +80,7 @@
    select UDK_202005_BINDING
    select DISPLAY_FSP_VERSION_INFO
    select HECI_DISABLE_USING_SMM
+	select SOC_INTEL_COMMON_PEP_S0IX

config MAX_CPUS
    int