Attention is currently required from: Lance Zhao, Michael Niewöhner. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48829 )
Change subject: soc/intel/*: drop UART pad configuration from common code ......................................................................
Patch Set 26:
(1 comment)
Patchset:
PS26:
The advantage of current implementation is people porting coreboot to different hardware not need to care about the detail mux setting just as simple as which uart port is using is good enough.
That is true, but the disadvantage is that one risks short-circuits if the setting is wrong. And if you look at the history of related Kconfig files, you'll see that it was more often configured wrong than right in the past. Oh, and the per-SoC tables were sometimes wrong too.
Please always consider that not everybody is working for a major vendor. If I break a board because of such misconfiguration, for instance, I have to wait weeks, for a new one to arrive.
There are other ways to make it more simple for newer ports. IMO, we should keep pad configuration in C code at the mainboard level to not lose track of it again. But it doesn't have to be per main- board pad tables. For instance, we could have per-topic/group pad tables at the SoC level. If you have any good idea how to design such code, please go ahead. I just needs to be less error-prone than the old Kconfig / SoC code mess.
And FSP will always program the GPIO pad base on uart selection base on FSP upd setting
What UPDs are those? I thought we agreed in the past that FSP shouldn't do any pad configuration?