Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36381 )
Change subject: mb/asrock/h110m: use SSDT generator for SuperIO
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Patch Set 3: Code-Review+2
Do you mean LPC IO ranges that are set using genX_dec in https://github.com/coreboot/coreboot/blob/master/src/soc/intel/skylake/lpc.c... ?
Those are the generic ones. For peripherals like the SIO or EC configuration access, IO-mapped serial, parallel and floppy disk controller ports the decodes can just be enabled by flipping the corresponding bits in the IO enable register in the LPC PCI device. If something can be covered by the specific ones, there's no need to use and basically waste a generic one for that
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