[coreboot-gerrit] Change in coreboot[master]: hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon

[Craig Hesling (Code Review)]

Craig Hesling has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37833 )

Change subject: hatch: Fix FPMCU pwr/rst gpio handling for dratini/jinlon
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37833/2/src/mainboard/google/hatch/... 
File src/mainboard/google/hatch/variants/dratini/ramstage.c:

https://review.coreboot.org/c/coreboot/+/37833/2/src/mainboard/google/hatch/... 
PS2, Line 30: 	mdelay(1);
> So why not take 500 μs?

That would probably be fine, but without testing the power rise time, I can't be sure.
I assumed that 1ms would probably account for any variance in temp, parts, and circuit-design.

I believe this sequence may be changed soon, anyways, since the reset line should to high-z'ed + we could probably rely on Power-on-reset. This was just the safest option, at the moment.