Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47398 )
Change subject: soc/intel/alderlake: Add PCIe root port wake sources to elog
......................................................................
Patch Set 1: Code-Review+2
--
To view, visit
https://review.coreboot.org/c/coreboot/+/47398
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483
Gerrit-Change-Number: 47398
Gerrit-PatchSet: 1
Gerrit-Owner: Tim Wawrzynczak
twawrzynczak@chromium.org
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Comment-Date: Tue, 10 Nov 2020 18:00:32 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment