[coreboot-gerrit] Change in coreboot[master]: Add configurable ramstage support for minimal PCI scanning

[ron minnich (Code Review)]

ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36221 )

Change subject: Add configurable ramstage support for minimal PCI scanning
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Patch Set 9:
> Patch Set 9:
> If my hunch about ACPI is correct here, and we eventually want to keep PCI enumeration without resource allocation, we are looking at 99% revert of this commit to fix it. Cases where vendors (and/or original authors) return to their code and willingly accept reverts are unfortunately rare. I did not fix the previous regressions I caused related to hidden Intel PCI devices either, I believe ultimately Nico committed the fixes(?).

So, kyosti, were we to add this mandatory struct member to the device struct (pick a name if you don't like that one) and in the MINIMAL scanning case, have the loop skip those devices not marked mandatory, is that approach one you would find workable?

I'm fine with that assuming I understand you correctly.

For the q35 target, it would be 0 lines of sconfig change, 2 lines added to two devices, and 2 lines added to the scan bus. Would this be something that makes more sense?

thanks.