Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41777 )
Change subject: soc/intel/jasperlake: add processor power limits control support
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41777/1/src/soc/intel/jasperlake/sy...
File src/soc/intel/jasperlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/41777/1/src/soc/intel/jasperlake/sy...
PS1, Line 69: mdelay(1);
Can you please add a comment regarding why the delay is required? Does BIOS reset CPL turn on some r […]
I see a similar delay is kept in all the SoCs. So I assume this is for legacy reasons.
--
To view, visit
https://review.coreboot.org/c/coreboot/+/41777
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib5502b225c1158c1f0729ce799ed0b8101f0233f
Gerrit-Change-Number: 41777
Gerrit-PatchSet: 1
Gerrit-Owner: Sumeet R Pawnikar
sumeet.r.pawnikar@intel.com
Gerrit-Reviewer: Aaron Durbin
adurbin@chromium.org
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Karthik Ramasubramanian
kramasub@google.com
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Tim Wawrzynczak
twawrzynczak@chromium.org
Gerrit-Reviewer: Todd Broch
tbroch@chromium.org
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-Comment-Date: Wed, 17 Jun 2020 22:25:58 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Karthik Ramasubramanian
kramasub@google.com
Gerrit-MessageType: comment